DS90UA101-Q1: DS90UA101-Q1 Configuration Issue

Has anyone had a chance to look at the request above?

Can you give a time frame as to when you might be able to provide the information?

Thanks for your help with this!

Richard Elmquist

Richard,
You can refer to the product documentation available online.

Why are they not wanting to configure the deserializer device? I am not sure if I follow why the BCK and LRCK needs to be supplied from the deserializer side.

I think this can be looked at offline, if you can send the block diagram and details about the application to the thread owner by email.

Palaniappan,
I will send you the diagram via email.
Thanks for your help with this !
Richard Elmquist

Darryl,
This is what I see from the diagram that he sent. The issue that I had is how would be receive these clocks on the serializer and use them with the digital microphones. Is his possible? I would have thought that the microphone would typically do this. It seems to me that the microphones would supply the necessary cocks in order to make sure that the data was aligned properly. If he is supplying them from somewhere else I do not know how he would actually be able to synchronize these microphones. Do you agree with my ideas here? Is it possible for the customer to do this application as shown in the drawing? Please let me know.
Thanks for your help with this!
Richard Elmquist

Darryl,
Have you had a chance to look at the questions I posed on the 11th?
Please let me know what you think so that I can respond back to the customer.
Thanks for your help with this!
Richard Elmquist

Hi Richard,

The microphone needs to be converted to I2S format (our chip does not do that)
The SCK must be provided by the source and it must also be synchronized with the LRCK and BCK for this to work.
Will the SCK for each microphone be independent?

Regards,
Darryl

Darryl,
I will find out the answers to these questions and post them is the customer still has any questions.
Thanks for your help with this!
Richard Elmquist

Darryl,

Here is an explanation of the setup rom the customer: 

Now to the synchronization: The BCK and the LRCK are synchronously provided by the FPGA which works as the data processing and communication to a computer. This BCK and LRCK is then provided on the pcb of the deserializer-side where they are transmitted into two differential pairs with the DS90LV049 and are driven by the drivers for the long Cat.7 trace. At the end of the trace they will be received by the equalizers on the pcb of the serializer-side. The BCK and LRCK are then driven by the transceivers SN74LVC245A to split up for the 8 microphones.

So the microphones will get the BCK and LRCK and will send their I2S-data to the serializer. The 4 I2S-data lines (8 microphones) will be inverted to provide a DC-balanced signal for the serializer, so that I have 8 I2S-data lines to the serializer. The BCK and LRCK will be send back too, but only because there are two more inputs available maybe to proof the signal, or to synchronize, or to check the delay at the deserializer’s output...

The required SCK for the serializer will be provided by the frequency-multiplier on the serializer pcb. So that is the reason why the SCK is synchronous to the BCK and LRCK which are provided on the pcb. The multiplier now works with a multiplication of 12 so that I get a frequency of 36MHz, synchronous to the BCK/ LRCK.

Then the serialized data will be driven by the driver and on the other end of the long trace received by the equalizer on the deserializer-pcb. The data arrive at the deserializer and will be transmitted into my 4 I2S-data, 4 inverted I2S-data and the transferred BCK and LRCK.

The deserializer first needs a SCK too. The SCK for the deserializer is provided by the frequency-multiplier on the pcb of the deserializer-side in the same way as on the serializer-side. But this multiplier uses the BCK of the FPGA! So we get a 36MHz SCK with a multiplication of 12, but consequently with a delay/ offset to the SCK of the deserializer-side. As I can see in the datasheets of the MAX9206 and counterpart DS92LV1224 in the section ‘Initialization’ both serializers and deserializers first lock on a ‘local clock, (my SCKs) which may be the same or separate’ with the internal PLL (datasheet of TI). When that is done and the serializer and deserializer is synchronized  ‘.. the deserializer detects edge transitions at the Bus LVDS input, (and) it will attempt to lock to the embedded clock information.’ This is the way how it should work and how it works in my case with a cable length of many meters (tested up to 50m), at least what I can see on the oscilloscope. But in the software after a cable length of 1 meter I get a bad/ big noisy signal. So as I said, I think this could be caused by the delay/ offset of the outgoing BCK of the FPGA and the incoming I2S-data. And I measured out that I have a delay of nearly 75ns with the ICs in sum and 1 meter of cable and maybe this is the limit for the software where it can detect the signal correctly.

Today I got a different FPGA-hardware and software where I can set a delay for the outgoing BCK and incoming I2S-data and I will test it. I will inform you about the new results.

Do you see any issues with the way he is setting this up and how he is “synchronizing” the clock? Is this probably the reason he is having problems receiving the signal even though he is using the equalizer. For reference you can use the high end drawing I sent earlier to show the position of the ICs that he is using.

Please let me know if you have any further questions for the customer.

Thanks for your help with this!

Richard Elmquist