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DS90UB926Q-Q1: Noise source of DS90UB926-Q1

Part Number: DS90UB926Q-Q1

Dear Support team

My customer are evaluating their prototype board with DS90UB926-Q1.

And they are thinking about the cause of noise in their board.

Is there any oscillator circuit that may make noise of 1.57GHz in DS90UB926-Q1?

■Condition

PCLK:37MHz

Data rate:1.295Gbps

Regards

Tomohiro Nagasawa

  • Hello,
    Are they seeing any performance issues in their system? Do they have any data to share about their noise measurements?

    Are they using the internal clock referenced below in the datasheet?

    From the 926 datasheet:
    The deserializer provides an optional PCLK output when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected. This feature is controlled by register Address 0x02, bit 5 (OSC Clock Enable). See Table 11.
  • Hello Manickeam-san

    Thank you for quick reposense.

    They does not use internal clock (OSC Clock disable setting)

    And they cannnot share noise data.

    If there is any other possibilities please give advice .

    Regards

    Tomohiro Nagasawa

  • If they cannot share noise data, what kind of performance issues are they seeing? We need to atleast know the background and why is the focus on the noise spur around this frequency. Are they testing for EMI/EMC performance?

    What serializer part are they using this 926 with and what type of cable and length? What does the PCLK jitter look like? By the way is this using the 926 EVM or one of their boards?

    Not following proper layout guidelines might be a cause for noise spurs, they can review the datasheet guidelines for any possible violations.
  • Hello Manickeam-san

    Thank you for response.
    They confirmed that noise is reduced by modifying the cable wiring and layout.

    Regards
    Tomohiro Nagasawa