DP83630: Basic questions about DP83630 and IEEE 1588.

Hello Kawai,

1. In question 1, do you mean to ask if the PHY stops using the X1 clock after receiving the PTP packet? No the system reference clock on X1 will still be used. The PTP packet is used to generate synchronized clock.

2. You might be using older version of the datasheet. Figure 6-1 in the updated datasheet deals with MDIO-MDC operation. If you are referring to the functional block diagram of the PHY with IEEE 1588 clock on GPIO pin then you are correct, it is used for IEEE 1588 clock output.

3. You are correct, these pins are required to be used between DP83630 and CPU.

-Regards,
Aniruddha

Hi Aniruddha-san,

Thanks for your quick support.

1). Using synchronized clock generated from PTP packet, MAC can be time synchronized with DP83630. If there are time difference (difference in synchronized clock) between master and slave, MAC/CPU can correct it in < nano second order through SMI. Am I correct ?

2). Sorry that I was looking at DP83640 Datasheet. In the datasheet of DP83630, it would be Figure 2-2. Can I understand that this IEEE 1588 clock output is synchronized with the 1PPS signal ?

3). Thanks for your comment.

I have one another question.

4). DP83630 generates IEEE 1588 clock output based on PTP packet. Does DP83630 dynamically optimizes the IEEE 1588 clock output itself based on the PTP packet receive timing or is the MAC/CPU software process is required ?

Best Regards,

Kawai

Hi Aniruddha-san and Team,

Could you please help me understand the device ?

Best Regards,
Kawai