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DS90UH940-Q1: Double Layer vs Multilayer Design

Fedor Adarichev
Prodigy 160 points

Part Number: DS90UH940-Q1
Other Parts Discussed in Thread: DS90UH949-Q1,

Hello,

My goal is to build a PCB with (2) DS90UH949-Q1's and (1) DS90UH940-Q1.  The PCB will also have an STDP4320.  The functionality of the circuit is to convert DisplayPort data to CSI-2.  So, there will be a couple of connectors, and I will have a CLK line, and I2C lines on the board as well.  My question is, for this board, will I need to implement multiple layers, or will a double layer, with the bottom as the ground plane, work?

  • 0
    TI__Expert 8165 points
    Hello-

    At least a 4-layer board is needed. Please check the device datasheets for more details.

    Regards,
    Davor
  • 0 in reply to Davor Glisic
    Prodigy 160 points

    I read over the datasheets for both chips and I did see the recommendations for PCB design.  However, in the interest of prototyping at lower cost, I am wondering if it is feasible to build a functioning board with just two layers, assuming I do not have PCB area limitations, and also that I will do my best to avoid placing different data traces close together?

  • 0 in reply to Fedor Adarichev
    TI__Expert 8165 points
    Hello-

    High-speed PCB design requires using interconnects (traces) with controlled impedance. For the FPD-Link III SerDes, you need 50-ohm single-ended and 100-ohm differential interconnects. With only two layers at your disposal, the bottom layer would be your GND reference for the signal traces on the top layer. For a 2 layer board, the thickness of the dielectric would be about 60 mils. With that, the traces would have to have ~120 mil (~3mm) widths to achieve 50-ohm single-ended / 100-ohm differential impedance. The traces would simply be too wide to interface to packages with 0.5 mm pitch.

    Regards,
    Davor