This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867E: PHY Setup

Part Number: DP83867E

I have a custom board which is configured exactly as the DP83867E EVK in snlu209.pdf, as far as PHY, Magnetics, and RJ45.  I have established MDIO communication using an FPGA, and can read and write registers.  I need to configure the board for SGMII operation, fixed 1Gbps.  Please confirm that Port Mirroring should be enabled, as the EVK (and therefore our custom board) have

PHY TD_A going to Magnetics TD4

PHY TD_B going to Magnetics TD3

PHY TD_C going to Magnetics TD2

PHY TD_D going to Magnetics TD1

I am programming registers

0x0000 = 0x0140

0x0009 = 0x0300

0x0010 = 0x5848

0x0011 = 0xA802

0x0014 = 0x2903

0x0031 = 0x0001 (using extended addressing)

But I do not get a link on the MD side.