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DS90UB914A-Q1: Behavior when DS90UB914A received 10bit data from 913A in 12bit mode

Tomoaki Yoshida91
Genius 5255 points
Part Number: DS90UB914A-Q1

Hi team,

Our customer is using 913A and 914A with 10bit mode.

They assume that 914's MODE pin short-circuits to GND due to some abnormality and is set to 12 bit mode.

When correct 10 bit data is sent from 913A, how will 914A handle this data?

In their experiments, there seem to be cases in which the 914A outputs data or does not output .

They hope that the 914A can judge that the data format is incorrect.

Otherwise, does the 914A handle the lower 10 bits of 12 bits and output data and sync?

Or will 914A sort 12bits as completely random data and output?

Best regards,

Tomoaki Yoshida

  • 0
    TI__Genius 10475 points
    Hello,
    What is the PCLK frequency? Can you explain about the MODE pin abnormality and which 12-bit mode is it being set to?
  • 0 in reply to Palaniappan Manickam
    Genius 5255 points
    Hi Palaniappan-san,

    Thank you for your support.
    PCLK is 94.5MHz.
    In abnormally situation, it was in 12bit LF mode.

    At that time, image was interrupted or images with disturbed color were output.
    So, communication is established intermittently, it seems that some data is being read.

    Best regards,
    Tomoaki Yoshida
  • 0 in reply to Tomoaki Yoshida91
    Genius 5255 points

    Hi Palaniappan-san,

    Any update on this issue?

    In this situation, how does 914A handle the image data on high speed forward channel?

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida91
    Genius 5255 points
    Hi Palaniappan-san,

    I want to know whether an error can be detected when the 914A receives the 10-bit mode image in the 12-bit LF mode setting.
    If it can not be detected by an error flag etc., I only have to see the output image, but I would like to know how data is handled at that time.

    Do you have any idea?

    Best regards,
    Tomoaki Yoshida
  • 0 in reply to Tomoaki Yoshida91
    TI__Genius 12866 points

    Hello,

    I am adding to my previous reply here. Since mode strapping only happens at device start-up, the processor could try to read 914 mode register 0x1F and determine if the correct mode is set. If not, the processor could override mode by writing to 0x1F which would solve this problem.

    914 does not have this error detection function. 913/914 relies on mode setting to switch between 10bit, 12bit LF, and 12bit HF. Each mode has different frame structures. 

    The max PCLK speed for 12LF mode is 50MHz. In your abnormal situation, the PCLK speed is too high which will cause data overflow. This is probably why you are seeing corrupted data or no data output. 

    If the PCLK is lower than 50MHz, in 12LF mode, 914 will assume the incoming data is in 12bit format.  If 10 bit data is supplied, 914 will only output these 10 bits +Sync.

    Best Regards,

    Charley Cai