Part Number: DP83867IR
Dear Sir/Madam,
I am using DP83867ISRGZR to design 10/100/1000 Ethernet port.
The 25MHz clock is from my FPGA output (2.5V square waveform). Before it goes to the DP83867, it goes through a one channel to multiple channel butter. The buffer output is also at 2.5V. From the buffer output it goes to DP83867 XI pin through a 33.6ohm series resistor. So, the clock at XI pin is 25MHz square waveform at 2.5V. XO pin is left open (NC).
According to the datasheet, if the clock is at 2.5V level, a capacitor divider (28pF in series, and 28pF to GND) to reduce its level to about 1.8V. Is this the recommendation or mandatory? Is the 2.5V clock input to XI pin going to damage the DP83867 device?
If we feed the 25MHz 2.5V square clock signal to XI pin directly, what's going to happen? With such design, we found that most of the DP83867 devices worked fine but a few of them did not work. For the non-working devices, they returned an invalid PHY ID when enquiring its ID. We probed the MDC/MDIO signals, their waveform and timing looked fine. We don't understand why the DP83867 did not return a valid ID. is it possible that the 2.5V clock did a bad thing to the device (e.g. damage) although most of the devices survived and worked fine.
What's the absolute input voltage level at the input to XI pin? Note that we are using 1.1V and 2.5V to supply the DP83867.
Our design is at critical path, your help support is greatly appreciated!
Thank you very much!
Wenbo
