• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 439 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS2553: Several questions

Hirotaka Matsumoto
Guru 27585 points
Part Number: TPS2553

Hi all

Would you mind if we ask TPS2553?

<Question1>
We have the question TPS2553-1(Latch off type).
How much is the response time to Short-Circuit or overcurrent?(2us?)
Otherwise, if there is 2us noise insertion, will TPS2553-1 be latch off?

<Question2>
FAULT deglitch on the datasheet, does it correspond for TPS2553-1(Latch off time)?

<Question3>
We have the question TPS2553(Constant-Current type).
In case of output current 0A - 0.7A - 0A - 0.7A - 0A - 0.7A 1ms interval with current limit=0.55A or 0.45A, what kind of action does FLT pin operate?
FAULT deglitch is min 5ms. So we assume that FAULT pin keeps high(no active).
Is our recognition correct?

Kind regards,

Hirotaka Matsumoto

  • 0
    Guru 27585 points

    Hi team

    We guess that your days are so busy, however could you let us know?

    Kind regards,

    Hirotaka Matsumoto

  • 0
    TI__Expert 8980 points

    Hi, Hirotaka Matsumoto,

    See my reply as below:

    <Question1>

    TPS2553/TPS2553-1 typical response time to Short-circuit or overcurrent is 2us. 2 us noise insertion will not make TPS2553-1 latch off, because this part is monitoring current to shutdown, not voltage. As below shows, current sense control driver to limit current/shutdown protection.

    <Question2>

    The TPS255x-1 asserts the FAULT signal during a fault condition and remains asserted while the part is latched-off. The FAULT signal is de-asserted once device power is cycled or the enable is toggled and the device resumes normal operation. The TPS255x and TPS255x-1 are designed to eliminate false FAULT eporting by using an internal delay de-glitch circuit for overcurrent (7.5-ms typical) and reverse-voltage (4-mstypical) conditions without the need for external circuitry(In datasheet, page14, 9.3.3).

    <Question3>

    It's correct. Deglitch time is to ensures that FAULT is not accidentally asserted due to normal operation such as starting into a heavy capacitive load. If overload condition last time< deglitch time, fault will not assert.

    Regards,

    Bob


  • 0 in reply to Hirotaka Matsumoto
    TI__Expert 8980 points

    Attached imagine for question1. If you can't see this imagine, please refer to block diagram at page 13.