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DS125DF1610: ds125df1610

cannie chang
Intellectual 910 points
Part Number: DS125DF1610


Hi, 

  I follow the procedure. yes, it can lock to 1.25G. thanks

I have another issue, your chip locking time is less than 100ms. when I have disruption about 30ms, does it possible freeze your CDR? 

Otherwise, my switch time will more than 50ms. Now, I measure the result is around 168ms. it seem does not make sense. max should be 100ms + 30ms. I use 3.072G to test it.

Does it have any setting can make CDR freeze at short disruption?

does TI has other chip can have shorter CDR time?

Thanks 

  • 0
    TI__Mastermind 29655 points
    Hi Cannie,

    Can you describe the disruption event? Is it an LOS (Loss of Signal) event, or is there some other noise signal inserted? To help us understand better, please let us know if there is a block diagram or scope shot you can share to describe this issue and how you measured it so that we can understand better what you are seeing.

    There is not a particular setting that is related to "freezing the CDR" for short disruptions in our products.

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    TI__Guru* 93570 points
    Hi Cannie,

    There are two ways to reduce CDR lock time:
    1). Use a setting with low number of divisors. Please refer to data sheet table 18. For example, for a divisor setting of 0x2F[7:4]=0x06 device goes through one divisor setting and this reduces CDR lock time.
    2). Secondly, device goes through different CTLE settings - reg 0x40 through reg 0x5F - to optimize incoming eye opening. Therefor if optimized CTLE setting is at for example 0x040 then device does not have to go through additional settings - which adds to overall lock time.

    Regards,,nasser