DP83867IR: TX_CLK is not coming

Moritz Julen

Part Number: DP83867IR

I am using DP83867IR EVM in 100Mbps MII Mode (GTX_CLK, RXD4..7 and TXD4..7 not connected). The CLKOUT pin on J8 is used as clock source for our design. RX_CLK is providing a 25MHz clock after forcing to 100MBps (disable 1000BASETFULLDUPLEX and 1000BASETHALFDUPLEX in CFG1). Link is established with 100M as expected. No data communication is possible. TX_CLK is driving '0' (tested with pull-up). Expected is a 25MHz clock output.

What could be wrong?

over 7 years ago

0 Geet Modi over 7 years ago

TI__Mastermind 26320 points

Hi,

Did you enable GMII interface (RX_D6 strap) ?

Regards,
Geet

0 Moritz Julen over 7 years ago in reply to Geet Modi

Prodigy 30 points

Hi Geet

Thanks a lot for your advise.

Your right. The bootstrap RX_D6 was floating. So RGMII is enabled. But the software disables the interface by writing a 0 into the RMGIICTL (0x0032) after soft reseting the chip. When I read back the register it looks correct. But the TX_CLK was still not working.
Only after soldering the boot strap resistor it works.

How can the RGMII interface be disabled by register settings? Do I have to follow a sequence?

best regards
Moritz

0 Ross Pimentel over 7 years ago in reply to Moritz Julen

TI__Mastermind 23675 points

Hi Moritz,

Any reset or power-cycle clears the register configuration.
Are you ensuring that the register is written after reset and power-cycle?

0 Moritz Julen over 7 years ago in reply to Ross Pimentel

Prodigy 30 points

Hi Ross

Thanks a lot for your answer. Your hint forced me to have a close view on this register.
I found a bug in the driver. The register access in the extended address space was buggy.

Now it works fine :-)

Best regards
Moritz

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DP83867IR: TX_CLK is not coming