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TPS65983B: Thunderbolt Questions

Richard Elmquist
Mastermind 45250 points
Part Number: TPS65983B

I have a customer who is developing a Thunderbolt 3 design with the TPS65983B. He has questions regarding the SPI interface and a bin file that he generated below:

1.  I'm working this with another engineer and he had a question too.  He put an Aardvark I2C from Totalphase on the line and he saw the I2C lines polling address 0x3F.  When he acknowledged that it quit.  Is that expected behavior?

2.  I was looking at the bin file generated by Intel when I add the TPS65983B code in.  It has pointers at 0x0 and 0xFFC like I would expect.  However there are none at 0x1000 or 0x1FFC.  Also the first set is pointing to the Region Pointer in the low header.  Is this okay or do the pointers need to be adjusted per the TPS65983 Firmware User's Guide?

Please let me know if you have any further questions for the customer.

Thanks for your help with this!

Richard Elmquist

  • 0
    TI__Mastermind 45250 points
    Has anyone had a chance to look at the request above?

    Can you give a time frame as to when you might be able to provide the information?

    Thanks for your help with this!

    Richard Elmquist
  • 0 in reply to Richard Elmquist
    TI__Mastermind 36756 points

    Hi Richard,

    1. When you have a brand new PCB with the TPS65983B, the SPI flash is empty. For the TPS65983B to boot correctly, it must have a valid full flash image in the SPI Flash. This can be programmed through the SPI interface on the Aardvark.

    2. For TBT designs, it is expected to use the Intel merge tool to combine the TPS65983B firmware with the intel TBT controller firmware so the two devices share the same SPI flash. These pointers are okay for this application.

    If this answers your question, PLEASE select  This resolved my issue

    Thank you,

    Eric

  • 0 in reply to Eric Beljaars
    TI__Mastermind 45250 points
    Eric,
    Thanks for your help.
    I will let you know if the customer has any further questions.
    Have a great day!
    Richard Elmquist
  • 0 in reply to Richard Elmquist
    TI__Mastermind 45250 points

    Eric,

    The customer has made the following comments:

    I can see both devices loading from the SPI flash at this point.  During the load, the Alpine Ridge sends I2C commands to the TPS65983B.  It consists of a write to 0x50 with data of 0x4 and a read from 0x5F of  0x04 0x83 0x00 0x01 and 0x06.  Can you provide an I2C register map including the bits that these registers contain (registers 0x50 and 0x5F)?

    Do we have a register map for this device? I did not see one in the data sheet.

    Thanks for your help with this!

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Mastermind 36756 points

    Hi Richard,

    This is expected behavior. 0x50 is the Data Control register and 0x5F is the Data Status register in the 83B. These registers are used by the TBT controller to determine the type of connection present. The Host Interface is similar to that of the 81, 82, 86 which can be found here:

    If this answers your question, PLEASE select  This resolved my issue

    Thank you,

    Eric

  • 0 in reply to Eric Beljaars
    TI__Mastermind 45250 points
    Eric,
    Thanks so much for your help!
    I will let you know if the customer has any further questions.
    Thanks again.
    Richard Elmquist