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DP83867E: RGMII LINK issue with an Ethernet switch

Shan Zhang
Prodigy 50 points
Part Number: DP83867E


Hi

I am using a DP83867E PHY on my custom FPGA board. If I connect my FPGA board to my PC directly, I am getting the throughput I wanted and things are looking fine on Wireshark. Only when I use a gigabit ethernet switch between my PC and custom FPGA board, I got lots of retransmissions on Wireshark and receive really low throughput. On PC side, I am running the iperf client with the same options (send data continuously for 10 seconds) in both cases, and FPGA firmware is exactly the same. The same throughput test I run on an Altera Dev Board (with a marvell 88e1111 PHY) was working fine with and without the ethernet switch. When I look into DP83867 Registers, I have the following register values.

Reg# With Ethernet Switch Without Ethernet Switch comment
0000 0x1140 0x1140
0001 0x7969 0x796D LINK STATUS: Not established with the switch
0002 0x2000 0x2000
0003 0xA231 0xA231
0004 0x01E1 0x01E1
0005 0xCDE1 0xCDE1
0006 0x006F 0x006F
0007 0x2001 0x2001
0008 0x6001 0x6001
0009 0x0300 0x0300
000A 0x38FF 0x7C00
000D 0x401F 0x401F
000E 0x0000 0x0000
000F 0x3000 0x3000
0010 0x5048 0x5048
0011 0xBC02 0xBC02
0012 0x0000 0x0000
0013 0x1C44 0x1C00
0014 0x29C7 0x29C7
0015 0x0001 0x0000
0016 0x0000 0x0000
0017 0x0040 0x0040
0018 0x6150 0x6150
0019 0x4444 0x4444
001A 0x0002 0x0002
001E 0x0002 0x0002
001F 0x0000 0x0000
0025 0x0400 0x0400
0031 0x10B0 0x10B0
0032 0x10D3 0x10D3
0033 0x0000 0x0000
0043 0x07A0 0x07A0
006E 0x0000 0x0000
006F 0x0000 0x0100
0071 0x0000 0x0000
0072 0x0000 0x0000
0086 0x0077 0x0077
00FE 0xE721 0xE721
0134 0x1000 0x1000
0135 0x0000 0x0000

LED_0  Strap pin (Mode 1)  ----- Mirrior Disabled and SGMII Disabled

LED_1 Strap Pin (Mode 1)  ----- ANEG_SEL is 0 and RGMII Clock Skew TX[2] is 0

LED_2 Strap Pin (Mode 1)  ----- RGMII Clock Skew TX[1] is 0 and RGMII Clock Skew TX[0] is 0

ANEG_DIS/EEE_DIS (RX_CTRL Mode 3) ----- I changed it from Mode 1 to Mode 3 because of this https://e2e.ti.com/support/interface/ethernet/f/903/p/490569/1789543 

CLK_SKEW_RX all open (Mode 1), as well as PHY Addreess (Mode 1)

My problem right now is that I can't get the throughput I wanted with the ethernet switch, I tried 3 different switches, with and without management interface, all having the same issue. As I mentioned earlier, the throughput test worked fine with and without ethernet switch on Altera Dev Board which has a different PHY chip. 

Thanks,

Shan Z

  • 0
    TI__Mastermind 26320 points
    Hi,

    The register dump shared with Swtich does not have link. However I beleive you are able to get the link and do packet transmission though observing retransmissions.

    Can you provide register dump "with Switch" where link is their and you have done some packet transmission ?


    Regards,
    Geet
  • 0 in reply to Geet Modi
    Prodigy 50 points
    Hi Geet,

    Thanks for your resposne. The PHY is configured as auto-negotiation, the LINK is always down whenever I connect it to my PC with a Switch. I tried to bring up the LINK by restarting auto-negotiation (writing to bit 9 at reg 0x0000), and still couldn't get the Link up. However, If I connect it without the switch, the link is always UP. Please let me know how I can get the link up mannually, so I can observe the tcp data transmission and provide you with a register dump.

    Notice the status register at 0x000a
    During auto-negotiation, the PHY is configured as MASTER without the switch, but act as Slave and receuved idle errors when connect it through an ethernet switch.

    Thanks,
    Shan
  • 0 in reply to Shan Zhang
    TI__Mastermind 26320 points
    Hi Shan,

    I think in your case seems like you are loosing the link while performing the data. Can you try forcing the DP83867 in slave mode and master mode both and see the stabilility ?

    You can do this using register 0x0093 : bit 11, 10.



    Regards,
    Geet
  • 0 in reply to Geet Modi
    Prodigy 50 points

    Hi Geet,

    So forcing DP83867E to Master mode work with one of the Ethernet Switches we have (Netgear GS105E). Before forcing the PHY to Master Mode, the LINK is not stable. (According to SNLA065A document, "When idle error count is high, approaching 0xFF, the link may
    drop and the GPHY will try to re-adapt with the link partner.") After forcing the PHY to Master mode, the link is UP and Stable, I was able to do the throughput test (~400Mbits/s for the normal packet)

    I also tried on couple HP ProCurve 1810G-8 switches (it supports Auto-MDIX), but the link is always down after forcing the PHY to master mode. 

    If I don't force it to Master mode when connecting to HP Procurve switch, the link status is not stable (link status toggling between Up and Down, and the counter at Reg 0x000a would continuously count up and reset). The RX_ER counter at 0x0015 will increase if I try to send the packet from my pc to FPGA when the link is not stable.

    So it seems like the PHY does not behave the same when connecting to different gigabit switches. How can I get the PHY to work consistently with different switches? 

    I didn't find register 0x0093 on the DP83867E datasheet, I forced the PHY to Master mode by modifying bit 11 and 12 on register 0x0009.

    Thanks,
    Shan

  • 0 in reply to Shan Zhang
    TI__Mastermind 26320 points

    Hi Shan,

    I also meant register 0x0009. by mistake '3' got added.

    On  HP ProCurve 1810G-8 switches, can you try two experiments :

    1. on Dp83867, disable Auto-MDIX and keep device in Slave Mode.

    2. On Dp83867, disable Auto-MDIX and keep device in master mode.

    Regards,

    Geet

    Regards,
    Geet

  • 0 in reply to Geet Modi
    Prodigy 50 points
    Hi Geet,

    I did run the following 2 tests you suggested on HP ProCurve 1810G-8 switch, and here's what I found.

    1. on Dp83867, disable Auto-MDIX and keep the device in Slave Mode.

    To disable Auto-MDIX, I wrote to bit 6 at register 0x0010 as instructed in DP83867E datasheet.
    The Link Status is not stable, counter at 0x000A is count up and then reset.
    ---------------------------------
    Reg Value
    0x0008 | 0x6801
    0x0009 | 0x0300
    0x000A | 0x38XX (counter value is keep changing)
    0x0010 | 0x5008
    0x0011 | 0xBC02
    ---------------------------------

    2. On Dp83867, disable Auto-MDIX and keep the device in master mode.

    The Link Status is always down.
    --------------------------------
    Reg Value
    0x0008 | 0x6801
    0x0009 | 0x1B00
    0x000A | 0x78FF
    0x0010 | 0x5008
    0x0011 | 0xBC02
    ---------------------------------


    Also, I compared the MDI crossover settings at register 0x0010 in master mode between Netgear switch and HP ProCurve switches.
    ------------------------------------------------------------------------------------------------
    Reg Netgear Value HP ProCurve Value
    0x0010 0x5048 0x5048
    0x0011 0xBC02 0xBF02



    Thanks,
    Shan
  • 0 in reply to Shan Zhang
    Prodigy 50 points
    Replaced the 25MHz clock oscillator (50 ppm) for the PHY chip on my board with a new mems clock IC (10 ppm), and things are working properly now.