I want to select a differential line receiver.
M application requires a differential line receiver,
capable of receiving: 1 (+) Pixel Enable, 1 (-) Pixel Enable, 1 (+) RS422 Pixel Clock, and 1 (-) RS422 Pixel Clock signals,
And outputting (to Frame grabber inputs): HSYNC and PCLK.
With the following additional comments:
Pixel enable +/- (8Khz TTL) should go to Hsync passing by a differential line receiver
and RS422 Pixel Clock +/- (variable rate from 7.5 Mhz to 15 Mhz) should go to Pclk after passing by a differential line receiver.
Technical support from the frame grabber (about what should be the differential line receiver output so that it can be a suitable input to the frame grabber) said the following: "Because you intend to use a fast pixel clock it will be an absolute requirement for you to use an LVDS format for the pclk, hsync and vsync."