Other Parts Discussed in Thread: DS32ELX0421
We have selected DS32ELX0124 for use in a large signage project, where we will daisy chaining multiple led panels with this ic (with CAT6 cable in between). Then I recently read in some threads here at the TI forum about a limit of how many devices that could be in series.
An example https://e2e.ti.com/support/interface/industrial_interface/f/142/t/638090
"There is ultimately going to be a limit the maximum number of deserializers, because there will be jitter peaking from the PLL of each CDR circuit, which will then accumulate in each redundant signal as it passes through more and more DS32ELX0124 deserializers."
This must be wrong? The whole idea with this chip is that it retimed signal is (almost) always in better quality than the incoming, with the (only) penalty of a delay.
The datasheet tells that the input has a 0.5 UI Minimum Input Jitter Tolerance, then the reclocked output must be WAY better and cleaned up than this, right ?
In the document http://www.ti.com/lit/ug/snla200/snla200.pdf , page 17 in bottom: "If achieving multiple daisy chain hops is a critical part of a given system, the DS32ELX0421/DS32ELX0124 FPGA-Link Ser/Des should be considered. The DS32ELX0124 FPGA-Link deserializer has an integrated re-timed loop-through driver with input equalization and output de-emphasis. The re-timer in the loopthrough cable driver circuit mitigates the jitter between each daisy chain hop, allowing for large numbers of daisy chain hops".
It contradicts the TI forum answer.
A "large numbers" indicates a lot more than only 16 devices, right?
What type of jitter is accumulating in each hop if the CDR in each hop already can recover a jitter of up to 0.5 UI?
So far we have not tested more than a few 4 hops, but with the above background I think we should soon perform a test of >25 hops and study the behaviour.
It would be very helpful to get a clarification of this issue, since our design depends on a "large numbers of devices daisy chain hops.
Thanks in advance.
/T
