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TCA8418: Minimum SCL and SDA fall times

Thomas Gundersen40
Prodigy 50 points
Part Number: TCA8418

Hi,

According to the TCA8418 datasheet minimum SCL/SDA input fall time(ticf) is 20+0,1*Cb. In my circuit Cb = 50 pF, so minimum ticf should be 25 ns. Unfortunately my minimum fall time is approx 10 ns(30/70%). My questions is:

  • What is the consequence(for TCA8414 and in general) of faster SCL/SDA fall times than the value in the datasheet? 
  • What is TI recommendations in order to "slow down" the fall times? 

  • 0
    TI__Guru 73271 points

    Hey Thomas,

    Before I answer the question I should point out that most of those requirements are pulled from the I2C standard. I could be wrong here but the minimum fall time could have previously been part of the standard (today the minimum fall time for fast mode is 20xVcc/5.5[ns]). The datasheet for this device looks like it was made in 2009 so I am wondering if the standard has changed for minimum fall time since then.

    "What is the consequence(for TCA8414 and in general) of faster SCL/SDA fall times than the value in the datasheet?"

    Some devices have slew rate detection which help it figure out if the line was pulled low, a really fast slew rate could be undetectable. Though MOST I2C devices probably don't have a slew rate detector for fall times. The two potential problems I see with a fast fall time is ringing on the signal when it transitions from high to low as this will cause a large undershoot that could fall below the absolute minimum voltage the device supports (our device is -0.5V). The second problem I could think of is this quick change in voltage over a small amount of time could result in a parasitic path where current can flow through parasitic capacitance on your board and inside of devices (I have never seen this issue pop up).

    I believe your faster than standard fall time should be okay as long as you don't see the large negative undershoot or notice any digital logic of devices acting funny.

    "What is TI recommendations in order to "slow down" the fall times?"

    I can think of two things that would slow fall time down. One is to increase the bus capacitance (a cap on the line to GND). The second is a small series resistor on the I2C bus. <-- I would be careful with this as this will also affect the VoL of the master and could also behave poorly if in front of a buffer with a voltage offset.

    Try placing a small resistor directly infront of the master (around 10 ohms to start) and you can slowly size it up. Be sure to check and make sure VoL does not get too large that the I2C devices can't detect a low.

    If you decide to mess with the bus capacitance, please remember the maximum allowed bus capacitance for 400kHz per I2C standard is 400pF.

    Thanks,

    -Bobby