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Original question:

DS90UB954-Q1: Parity check and CRC error

DS90UB954-Q1: Parity check and CRC error

Ellis Miller
Prodigy 30 points
Part Number: DS90UB954-Q1
Other Parts Discussed in Thread: DS90UH948-Q1

Related to the CRC errors we are using the DS90UH948-Q1 paired with 949.  The back channel is not connected but we are experiencing CRC errors over time.

Does the CRC have to be reset or what keeps the CRC in sync so there are not CRC errors. The error does not happen for 3-4 hours of operation, could there be a self calibration

issue, parity issue over time??

  • 0
    TI__Genius 10475 points
    Are you able to get reliable LOCK on the link? Are you monitoring the back channel CRC errors?
    You can look at the device datasheets for additional information on back channel CRC error registers and BIST mode which you can use to validate the link.
    There are registers to reset the CRC error counters which you can use to check if the errors are re-occuring.
  • 0 in reply to Palaniappan Manickam
    Prodigy 30 points

    Palaniappan,

    We have lock and the FPD link and I2C bus works great for several hours or days. We are running 5 MBP’s on the back channel, we are using the errata method from TI which does not use BIST mode. The system begins to show many CRC errors and then becomes slow or non responsive but lock remains on the FPD link. 

    Ellis

     

  • 0 in reply to Ellis Miller
    Prodigy 30 points
    Also we are monitoring the CRC to help us with the snow issue witnessed in some FPD link chipsets running at 1080P. If we see 10 - 12 CRC errors within 20 seconds we reset the deserialser 948 per the errata. The errors seem to only effect the I2C bus slowing it down..
  • 0 in reply to Ellis Miller
    TI__Genius 10475 points
    Not sure if I fully understand what the issue is. So no issue seen with the link data integrity and LOCK looks normal but after several hours or days there are back channel CRC errors that affects proper I2C operation?
    What 948 errata are you referring to?