Part Number: DS92LV1212
In the current design we are using DS92LV1212AMSA-DS92LV1021AMSA pair for sending parallel ADC data through galvanicaly-isolated barrier. On the receiving side we process these data in a FPGA.
Now we are in the phase of re-design and will use much bigger FPGA which will (in theory) allow use of internal SERDES receiver instead of DS92LV1212.
The only thing that is missing are SYNC patterns used during synchronization phase which I can't find anywhere. Can you help me there?
