Other Parts Discussed in Thread: SN75LVDS83B, DS90C387A, SN65LVDS93A
Hi ,
As per the data sheet of TFP401A pin no.4 PIXS
Pixel select – Selects between one- and two-pixels-per-clock output modes. During the 2- pixel/clock mode, both even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During 1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel). High: 2-pixel/clock Low: 1-pixel/clock
In 2 Pixel Per clock mode First Pixel is Odd and Second Pixel is even but when we refer below link the design suggestion is reverse can you please explain us.

Thanks in advance.
-Amit Jain