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HD3SS3415: PCIE MUX ：HD3SS3415 Cascade Problems

yong zhao
Prodigy 10 points
Part Number: HD3SS3415
Other Parts Discussed in Thread: DS80PCI810

The GPU Server Which Support Intel  Purley   2S  Platform , and Combine 2  PLX8796 PCIE Switches. Implementing CPU0/CPU1 PCIE root switching through TI HD3SS3415 , Which Tuopu as blow:

1.With a two-stage PCIE MUX：HD3SS3415, is this solution feasible and can you implement PCIE free switching?

2.The length of the PCB trace has been marked as follows. After the CPU0 or CPU1 passes the two stages of the PCIe MUX：HD3SS3415, the PCIE SWITCH PLX8796 is reached. Can the signal rate reach 12Gb/s?

3.Need to add PCIE RE-DRIVER?

4.Is there a delay in PCIE signal transmission?

  • 0
    TI__Mastermind 29655 points
    Hi Zhaoyong,

    I assume that you will be designing with a PCIe Gen-3 application.

    1. Your 2-stage architecture should work for your switching applications, as these switches are passive and thus should not cause an issue with cascading. Seeing that the GPU server requires a x16 lane width, you will need multiple 4-channel HD3SS3415 switches for each "PCIE MUX" block in your system. Note that you will incur up to -1.5 dB loss at 4 GHz as the signal passes through each HD3SS3415.

    2. The HD3SS3415 is rated for operation up to 12 Gbps, but the data rate depends on the CPU in your system. Since this is a PCIe application, the rates going through the HD3SS3415 should not exceed 8 Gbps at Gen-3. Is there a concern you have for 12 Gbps operation?

    3. I would advise a redriver such as the DS80PCI810 for the section of your diagram titled "PCIEX16_MUX." This will help with insertion loss due to the 10" and 7" traces before the first mux.

    4. There will be at maximum 85 ps propagation delay through the switch, which is about 50-55 ps longer than when the signal travels through just trace. Please let me know if there was a more specific question you have about delay.

    Thanks,

    Michael