• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 34 subscribers
  • Views 1407 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB914A-Q1: Adaptive Equalizer Details

Kenichiro
Mastermind 9165 points

Part Number: DS90UB914A-Q1

THIS IS RELATED TO THE ISSUE OCCURRING AT ONE OF MAJOR OEM NOW.

[ DS90UB914A-Q1 ] Adaptive Equalizer Details

Hi,

Can you please elaborate how adaptive equalizer operate on DS90UB914A-Q1?

<Q1>: Start-Up / Restart

After power up of DS90UB914A-Q1 or refume from loss of lock condition, how can device find a best EQ setting?
Does it start either from minimum or maximum EQ setting?
What is the condition to select the best EQ setting?

<Q2>: Gain Accuracy / Variation

There is no specification related to the gain accuracy and/or variation compare with the value specified in resigter table below.
Do you have any of numbers, ranges or indication of this variation?



<Q3>: Possible AEQ Failure and CMLOUT of PRE-AEQ

Can we expect the failure of AEQ? Let's say, the AEQ function in several devices would have worse equalization performance. That finally cause the received signal degradation. Is that a case?

Also, we have CMLOUT pins to make sure the signal of post AEQ. Do we have any ways to check the waveform pre-AEQ?

Thanks,
Ken

<Other Good Reference, Before Posting>:


[ DS90UB914A ] Registers
e2e.ti.com/.../350587

DS90UB914 Eq settings
e2e.ti.com/.../382092

DS90UB913A/914A receive error with 2m cable
e2e.ti.com/.../529101

  • 0
    TI__Genius 10475 points
    Ken,
    Can you provide more information/background on the issue and what they are seeing?

    1. What is their channel length and loss and what type of cable?
    2. What is the line rate and PCLK frequency?
    3. Are they using AEQ or manual EQ setting? (Register 0x4D[6] and register 0x04[7:4] controls this)
    4. Is the behavior only on one or specific no of devices and is it repeatable?
    5. What is their device power up/system start up sequence?

    Are they meeting the power-up requirements and PDB pin as per section 9.1.2 in the datasheet?

    Also it is important to follow the proper system level startup sequence - i.e. the 914A should be reset with the proper signal present at the input from the serializer so the AEQ can perform optimally and lock to the correct values. This can be done via either PDB pin or digital reset 1 via I2C.

    Please refer to the DS90UB914A device datasheet section 9.1.4 and 9.1.5 for information on channel loss, channel requirements for 913A/914A and AEQ loss compensation.
  • 0 in reply to Palaniappan Manickam
    Mastermind 9165 points

    Hi Palaniappan,

    Thank you for your comment. I will come back to you with some more details later.

    Let me ask quick one. Do we have any signal path other than CMLOUT to capture the signal before AEQ?
    (Added: may be after backchannel separation and before AEQ)

    Thanks,
    Ken

  • 0 in reply to Kenichiro
    TI__Genius 10475 points
    Ken,
    No, CMLOUT monitors the post-AEQ stage i.e. after adaptive equalization.
  • 0 in reply to Palaniappan Manickam
    Mastermind 9165 points

    Hi Palaniappan,

    > 1. What is their channel length and loss and what type of cable?

    We know their cable length (>10m), however, we have not performed its insertion loss measurement.

    > 2. What is the line rate and PCLK frequency?

    10bit mode with around 60MHz PCLK, thus line rate would be 840Mbps.

    > 3. Are they using AEQ or manual EQ setting? (Register 0x4D[6] and register 0x04[7:4] controls this)

    My customer use AEQ
    Yes, it would be reasonable to check CMLOUT waveform with various 0x04[7:4] settings.

    > 4. Is the behavior only on one or specific no of devices and is it repeatable?
    (A question below is quoted from the other post)
    > Have they done A-B-A swap to switch the known good unit between boards to see if the failure follows the unit or the board?

    So far, we have seen this behavior only on two units which have 100% repeatability.
    Before performing ABA swap, we have spent time for more debugging...

    > 5. What is their device power up/system start up sequence?

    Follow the sequence in the datasheet.



    So far, we have tried to identify the issue is related to particular units or something like the application issue(their schematics, layout...).
    Still few discussion going on and we are a bit concerned the disappearing behavior be removing and mounting for swap test.

    Thanks,
    Ken

  • 0 in reply to Kenichiro
    TI__Genius 10475 points
    If there is no update or no further questions let me close this thread.