PCA9544A: PCA9544 keeps SDA low on a read

Hey Ian,

Can you provide scope shots of the communication before and during the read when you see the SDA line latch low?

Are you able to pulse the SCL line with 9~18 clock pulses and then able to check to see if SDA unlatches?

"What can cause this to happen?"
It could be possible to cause this if the device's state machine was glitch during communication. For example, it see's its address and ACKs but never sees a raising edge to the 9th clock cycle (cycle where the ack is expect) so it will not release until it sees a new clock cycle.

This device is a switch so I am also wondering if it's possible that one of the slaves on the other side of the switch is holding the line low. Are you able to only power cycle the switch and check SDA lines on the other channels to make sure SDA was not stuck before the channel was even enabled?

Please also check the rising edge of VCC when you turn on the device. Section 11 of the datasheet discusses a known issue with a bad power on reset that can cause the device to glitch though usually this is not the kind of issue that comes up.....

Let me know your findings.

Thanks,
-Bobby