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Linux/DS90UB954-Q1: DS90UB954A sends unnormal mipi signals

luke lan
Prodigy 130 points
Part Number: DS90UB954-Q1

Tool/software: Linux

Hi,

we got some problems when using DS90UB954A forward FPD-LINK siganl.
On receive side, soc may received unnormal mipi signal.

Hardware structure as below:
sensor => [913] ==> coax-FPD-LINK==> [954] ==> mipi==> SOC

And Sensor outputs:
1280x720@30fps YUV422 BT601

This issue occurs shortly after system booted. At first soc could
receive right image and then it will stop. Under this situation,
mipi sinal like this:

mipi_error.tar.gz

Some times, soc could not could not decode mipi signals. And from
oscilloscope views, we are not sure signal is normal or not. so we
hope TI to help us to analyse these signals.

  • 0
    TI__Genius 10475 points
    Hello,
    What imager is this and have you verified the imager is getting initialized properly? Do you have a CSI analyzer to verify the CSI-2 packets coming out of the 954?
    You can use the pattern generator in 954 to verify the 954 to SoC path is working correctly.
  • 0 in reply to Palaniappan Manickam
    Prodigy 130 points
    Hi Palaniappan Manickam,

    Thanks your advises and all your proposes we had consider seriously.

    1. What imager is this and have you verified the imager is getting initialized properly?
    　　The sensor we used is: Sony ISX 016. We almost sure it works fine, because signal can be detected on coax.
    [sensor] ==> coax ==> [913]

    2. Do you have a CSI analyzer to verify the CSI-2 packets coming out of the 954?
    There is no CSI analyzer for us to debug. And mipi protocol is too difficult for us to review. TI will be more famillar than us to review it, cause we have no idea about 954 signal producer.

    3. You can use the pattern generator in 954 to verify the 954 to SoC path is working correctly.
    Under this situation, SoC try to let 954 switch to color-bar mode but the unnormal signal seems to no change. And reset 954 is also helpless.
  • 0 in reply to luke lan
    TI__Mastermind 30515 points
    please share your comments if resolved.

    For your picture, you should measure the high speed diff. signals with ~200mV peak in single-end, and ~1.8V in the LPS.

    best regards,
    Steven
  • 0 in reply to Steven(Shenzhen) Shi
    Prodigy 130 points
    Hi Steven,
    There are some unnormal cases that mipi signal with ~400mV peak in single-end, and no images SoC side could
    get. Under normal state, it will keep +- 200mV and system works fine. Any factors may cause such problem?
  • 0 in reply to luke lan
    TI__Mastermind 30515 points

    Hi Luke,

    how many parts do you have the output test issues? all are tested in the same setup and same board?

    based on MIPI compliance test procedure, it should have correct output matching network to meet the HS and LPS switching, please confirm that the on-board CSI2 data and clock have correct matching design.

    If it is confirmed that Chip has output swing issue, please contact with TI's engineer for failure analysis.

    best regards,

    Steven