SN65DSI85: SN65DSI85 register (PLL_EN /PLL_EN_STAT)(SYNC_DELAY)(register Test Pattern Generation Mode)?

PHILIP HSU

Expert 1900 points

Part Number: SN65DSI85

Hi Sir

customer would like to get SN65DSI85 relatives :

Q1: is it possible for default "0" setting change to timming register,.?

Q2:What`s different to PLL_EN between PLL_EN_STAT ?

Q3:What`s purpose of RIGHT_CROP and LEFT_CROP and how measure it ?

Q4: Any description for LVDS_CLK_RANGE
                                     DSI_CLK_DIVIDER
                                     CHA_DSI_CLK_RANGE
                                      CHB_DSI_CLK_RANGE

Q5: What`s setting value of SYNC_DELAY ?CSR 0x28.7:0 to 0x20？

over 7 years ago

0 Ikechukwu Anyiam over 7 years ago

TI__Mastermind 35130 points

Hi Philip,

We'll look into these questions and get back to you soon.

Regards,
I.K.

0 PHILIP HSU over 7 years ago in reply to Ikechukwu Anyiam

Expert 1900 points

Any update ?

0 Ikechukwu Anyiam over 7 years ago

TI__Mastermind 35130 points

Hello Philip,

Sorry for the delay.

Q1: I'm not sure I understand this question. Can you specify the register address?

Q2: PLL_EN_STAT is the status of the PLL, and whether it's enabled or not. It is a read only register. PLL_EN is the register you write to to enable/disable the PLL.

Q3: Please see Table 11 on page 30 and 34 of the datasheet for a description of RIGHT_CROP and LEFT_CROP.

Q4: Please see the register map in section 8.6 of the datasheet for a description of these parameters.

Q5: Yes, that's correct.

Regards,

I.K.

0 PHILIP HSU over 7 years ago in reply to Ikechukwu Anyiam

Expert 1900 points

Hi Sir,.

please refer the attached .dsi file from tool, please tech us the error time line ,..

thank you

the register. of E5、E6

1. HFP = 32，LVDS is unavalible

Read SN65DSI85 REG=0XE5 ,Value=0x81

Read SN65DSI85 REG=0XE6 ,Value=0x20

1. HFP = 232，LVDS is avalible

Read SN65DSI85 REG=0XE5 ,Value=0x01

Read SN65DSI85 REG=0XE6 ,Value=0x20

CSR and DSI.zip

0 Ikechukwu Anyiam over 7 years ago in reply to PHILIP HSU

TI__Mastermind 35130 points

Hello Philip,

In the clock section you have the LVDS CLK setting as 75MHz, but the divisor value you have chosen for the DSI CLK results in an LVDS CLK of 30MHz. Please set the divisor to 4 if your LVDS CLK is 75MHz and your DSI CLK is 300MHz.

Regards,

I.K.

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SN65DSI85: SN65DSI85 register (PLL_EN /PLL_EN_STAT)(SYNC_DELAY)(register Test Pattern Generation Mode)?