DS92LV18: Correct way of clock management

adrien besserve

Part Number: DS92LV18

Hi,

I am working on a design with full duplex LVDS Ser/Des using DS92LV18. (Let's call Side 1 and Side 2 the two LVDS side in point to point bidir full duplex operation)

Side 1 has a FPGA that manage clocks TCLK and REFCLK.

Side 2 only has an oscillator generating REFCLK (5% max of TCLK). For the TCLK of side 2, I wonder if it's better to use either autogenerated clock : RCLK ou to also use the oscilator that generate REFCLK.

What would be the best practice according to you ?

Best regards

Adrien

over 7 years ago

0 Lee Sledjeski over 7 years ago

TI__Mastermind 43795 points

Adrien,

I would prefer to use the oscillator clock to provide a synchronus clock domain on side 2. The output clock of the deserializer can accumlate jitter which will make recovery on side 1 slightly more difficult. This situation gets worse with multiple Ser -> Des -> Ser hops daisy chained together.

Regards,

Lee

0 adrien besserve over 7 years ago in reply to Lee Sledjeski

Prodigy 50 points

Thanks for advise !

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DS92LV18: Correct way of clock management