I am trying to get more information on lock time. Does anyone have measured lock times?
The datasheet states that the lock time is "From signal detected to the lock asserted". What exactly defines "signal detected" and is there a time estimate for that?
The reason I ask is because we're looking at a similar architecture using an FPGA/VCXO, and most VCXOs I've looked at, have lock times in the hundreds of milliseconds.
