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SN65DP159: can I apply data_lane to in_clk circuit in straight throught mode?

lam huynh
Prodigy 190 points
Part Number: SN65DP159
Other Parts Discussed in Thread: TDP158

Hello,

Reading specs of DP159:

In section 7.6 diff inputs characteristics says that max clock lane rate = 340 MHz

In Figure 24: with SWAP = L it shows that data_lane2 is applied to IN_CLK pins

These 2 info are kind of contradicting.   I would like to use the DP159 with data_lane2 to IN_CLK, data_lane1 to IN_D0, data_lane0 to IN_D1 and clock_lane to IN_D2 but in normal working SWAP =Z (straight throught).  Is it possible when my data_lanex rate is ~ 5Gb/s?   

Thanks

Lam Huynh

  • 0
    TI__Guru 64326 points
    Lam,

    This configuration is possible because all lanes of SN65DP159 are electrically equivalent. The clock lane is specified this way because of the PLL associated the clock lane. So in SWAP =L mode, IN_D2 has a max of 340 MHz because the PLL is associated with IN_D2 and feeds the output to OUT_CLK.
  • 0 in reply to Malik Barton57
    Prodigy 190 points

    Hello Malik,

    I would understand the electrically equivalent part, it makes sense to design one path and copy 4 times.  Could you elaborate more on the "PLL associated the clock lane"?  Does it mean the OUT_CLK will always be limited to 340 MHz and cannot handle 6Gbps?

    In my application, I want the DATA_LANE2 to output on the OUT_CLK and if it cannot handle 6Gbps then the application fails.  Essentially, I use the DP156 as sink receiver and its input pins are not lined up with HDMI connector pins when mounted on same layer as DP159.

    Another question: If I apply data_lane2+/- to pins IN_CLKn/p and get data_lane2+/- out of OUT_CLKn/p, it does not count as polarity swap, isn't it?

    Thanks

    Lam

     

  • 0 in reply to lam huynh
    TI__Guru 64326 points

    Lam,

    1) Q:Does it mean the OUT_CLK will always be limited to 340 MHz and cannot handle 6Gbps?

        A: Yes it is limited in retimer mode because of the PLL. The PLL allows for the retiming capability of the part and is not specified to lock onto a 6 Gbps clock. SN65DP159 clock lane output is specified at a max of 340 MHz for retimer mode because in this mode it is always connected to the PLL. Refer to image below from datasheet.

    2) Q:If I apply data_lane2+/- to pins IN_CLKn/p and get data_lane2+/- out of OUT_CLKn/p, it does not count as polarity swap, isn't it?

        A: No I believe that this situation is not polarity swap by the device. If SN65DP159 polarity swap is implemented, data_lane2+/- to pins IN_CLKn/p would result  in data_lane2-/+ to pins IN_CLKn/p. In order to do this the polarity swap bit must be set appropriately. 

     Are you using the part in Retimer mode or Redriver mode? If you are using it in Redriver mode, I suggest using TDP158 which may be better for a source side application. 

  • 0 in reply to Malik Barton57
    Prodigy 190 points

    Hello Malik,

    I want to confirm again:

    2) Q:If I apply data_lane2+/- to pins IN_CLKn/p and get data_lane2+/- out of OUT_CLKn/p, it does not count as polarity swap, isn't it?

        A: No I believe that this situation is not polarity swap by the device. If SN65DP159 polarity swap is implemented, data_lane2+/- to pins IN_CLKn/p would result  in data_lane2-/+ to pins IN_CLKn/p. In order to do this the polarity swap bit must be set appropriately. 

    Reason is that polarity inversion works only in retimer mode, and we want to keep flexibility of operating either as a redriver or retimer.

    Another question:  TMDS has signal detection block on the HDMI_CLK input pair, if I do lane swap and feed HDMI_data#2 to those inputs, is the signal detection block still operational?

    Thanks

    Lam

  • 0 in reply to lam huynh
    TI__Guru 60870 points
    Lam,

    This won't work, the redriver / retimer can swap which input it is expecting the CLK signals to be received on, but it cannot swap the outputs. The output clock is always on pins 25 and 26.

    Regards,
    JMMN