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DP83822I: DP83822I, RGMII, RX CLOCK

Iven Xu
Intellectual 2090 points
Part Number: DP83822I

Hi expert,

I would like to ask a question about the RGMII mode in DP83822I, you can see the figure 11 in datasheet.

1, how to add this internal delay if customer's pcb design use the equal line layout?

2, in below figure: what's the main reason for adding this delay? i am thinking when RX_CLK (at transmitter) which cannot be used as the reference DDR clock for data transmission,right?

3, so customer have to add the delay when RX clock going out from the PHY, such as the dot line clock in RX_CLK(at transmitter) waveform?

4, what's the meaning of the RX_CLK(at receiver) in below figure?

Best Regards

Iven Xu

  • 0
    TI__Mastermind 26320 points

    1. Kindly refer to  Table 38. 0x0017 "RMII and Status Register (RCSR)". Phy provides options to adjust both Rx and TX Clock 

    2.  That's correct, it a DDR signal.

    3. RX_CLK is clockout from Phy and input to MAC. MAC usage this to sample the data.

    Regards,
    Geet

  • 0 in reply to Geet Modi
    TI__Intellectual 2090 points

    Hi Geet,

    thanks for your response. but could you please be more details to answer my questions? thanks.

    2, I understood RX_CLK is the DDR clock, but what's the different RX_CLK(at transmitter) and RX_CLK(at receiver) in figure 11?

    3, What's the dot line clock in RX_CLK(at transmitter) waveform in figure 11?

    4, What's the meaning of the RX_CLK(at receiver) in below figure, I found it is different with with the RX_CLK(at transmitter), is it caused by the pcb transmission?

    Best Regards

    Iven Xu

  • 0 in reply to Iven Xu
    TI__Mastermind 26320 points
    Hi Iven,


    RGMII specifications requirements Transmitter to provide data and clock aligned with in +/- 500 ps. However to sample the data properly on reciever, skew between data and clock shall be 1.8ns +/- 0.8ns. To achieve the delay, two methods are followed:

    1. Use pcb layout to insert the skew between clock and data.
    2. Phy provides register configuration to insert the delay at reciever.

    To answer your questions:

    1. RX_CLK shown (as transsmitter) is output of the Transmitter aligned with data.
    2. dot line is option provided by Phy to delay the clock at transmitter and avoid pcb layout based solution
    3. RX_CLK ( at reciever) : expected skew between data and clock.


    Hope it clarifies.

    Regards,
    Geet
  • 0 in reply to Iven Xu
    TI__Intellectual 2090 points
    Hi Geet,

    one more question:
    you mentioned that the "RGMII specifications requirements Transmitter to provide data and clock aligned with in +/- 500 ps, so which need add the delay (skew) to make sure the receiver can capacture the data correctly"

    question: how about the RMII and MII? do they also have the similar specifications requirement?

    best regards
    Iven Xu
  • 0 in reply to Iven Xu
    TI__Mastermind 26320 points
    Speed on MII and RMII are lower, hence the spec are not very tight.

    Regards,
    Geet
  • 0 in reply to Geet Modi
    TI__Intellectual 2090 points
    Hi Geet,

    got it, thanks for your quick response.


    Best Regards
    Iven Xu