Hi,
Where did the values of Min_SR, Min_HR, IO_skew in table 3 of snla243 come from? They are not in the DP83867E datasheet. In the datasheet, T_setupR and T_holdR is 1ns. If we use Min_SR = 1ns and Min_HR =1ns in equations 1-4, the set up and hold margins are not positive:
(1) t_sr = t_id - ID_var - T_skewT - IO_skew - PCB_skew
(2) Setup Margin = t_sr - Min_sr
(3) t_hr min = tchmin - t_id - ID_var - T_skewT - IO_skew - PCB_skew
(4) Hold Margin = t_hr - Min_hr
t_id = 2.0ns (mode 0 strap)
ID_var = 0.2ns (from snla243)
IO_skew = 0.35ns (from snla243)
Min_sr = (datasheet says 1ns)
Min_hr = (datasheet says 1ns)
PCB_skew = 0.01ns (lowered from snla243)
T_skewT = 0.5ns (from rgmii v2 spec in snla243)
tchmin = 0.45*8ns = 3.6 ns
(1) t_sr = 2 - 0.2 - 0.5 - 0.35 - 0.01 = 0.94 ns
(2) Setup Margin = t_sr - Min_sr = 0.94 - 1.0ns = -0.06ns
(3) t_hr min = 3.6ns - 2 - 0.2 - 0.5 - 0.35 - 0.01 = 0.54
(4) Hold Margin = t_hr - Min_hr = 0.54 - 1.0 = -0.46
I've tried adjusting the delay by increments of 0.25 ns, but it's not possible to get the set up and hold margins positive using the above numbers from snla243. The IO_skew of .35 ns and ID_var of 0.2 ns are too large.
Why is the I/O buffer skew (IO_skew = 350ps) so large? Also, why is the internal ID_var so large (200ps)? Are these typos? It doesn't seem possible to get positive margin while using the internal delay. Any information/guidance would be much appreciated.
Thanks!