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DS90UB927Q-Q1: screen will shake

Piero Yu
Intellectual 950 points
Part Number: DS90UB927Q-Q1

Currently ctm used  927 and 928 for transmission lvds data, lvds resolution is 1024X768;
         The specification of the screen: clk is between 57.5Mhz and 74.7MHz
         Our frame rate must be above 55fps to meet the lvds screen requirements;
         Will 927 and 928 meet the bandwidth requirements? The current screen will shake. The screen is 1344*806

  • 0
    TI__Genius 10475 points
    Hello,
    You can refer to the FPD-Link device datasheets for supported rates and PCLK frequencies.
    Can you provide more information about the screen shake?
  • 0 in reply to Palaniappan Manickam
    Intellectual 950 points

    the PCLK is set as 65.9M,which can use oscilloscopes to measure RxClkin pins: 40Mhz to 150Mhz, constantly changing,very fast.

    When the frame rate set as 55fps, the screen shake as the attached vedio.

    But when set frame rate as 40fps, the screen just shake occasionally.

  • 0 in reply to Piero Yu
    TI__Mastermind 30515 points
    Hi,
    1. if the screen is 1344*806@55fps, how can you calculate the PCLK is ~65.9MHz? can you try the pclk with 1344x806x55=~59.6MHz?
    2. from the failure symptom, it seems the link is not stable, can you measure the LOCK pin of UB928, does it be toggled? please check the link jitter margin design to improve the reliability. thanks.

    best regards,
    Steven
  • 0 in reply to Steven(Shenzhen) Shi
    Intellectual 950 points

    Sorry, it was 1344x806x60=~64.9MHz.

    Yes, the Lock pin is toggled when the screen shaked.

    So can 928 support 1344x806x60？ And how to  check the link jitter margin design to improve the reliability?

    Pls help,thanks.

  • 0 in reply to Piero Yu
    TI__Mastermind 30515 points
    please follow up the high speed link design rule:
    1. test the pclk jitter which is required in d/s
    2. please evaluate the cable and connector SI performance, how about the characteristic impedance, S11 and S21?
    3. please measure the CMLout eye-diagram from UB928. it ahs one refer. spec in d/s
    btw, how about the failure rate?

    best regards,
    Steven
  • 0 in reply to Steven(Shenzhen) Shi
    Intellectual 950 points

    Sorry, How to test the pclk jitter ? Which pin?

  • 0 in reply to Piero Yu
    TI__Mastermind 30515 points

    Piero,

    You can check the d/s page9 on tolerance jitter spec., you can measure the rxclkin+/- pins, thanks.

    best regards,

    Steven