Hello.
I connect Xilinx's Zynq-7000 and DP83867IS (CS) and are doing RGMII communication.
There is a problem that Ping packets exceeding 100 Bytes can not be sent.
･ Zynq-7000
It uses PL general-purpose I / O (LVCMOS 25), and the internal module uses "GMII to RGMII" built in by default.
･ DP83867 IS
The I / O voltage is 2.5 V, and all the strap settings are "MODE 1".
* "RX_CTRL" should be set to MODE 3, but changing it did not solve the problem.
I have found a few things that may be the cause of this problem.
･ Near-end noise and far-end noise (overshoot, undershoot) were found on the rising edge or falling edge of the RGMII clock signal and data signal.
･ Impedance matching is not implemented on the RGMII path. (Equal-length wiring is implemented, but the wiring length is slightly longer (120 mm))
･ There are two vias between Zynq-7000 and DP83867IS for RGMII routes. (The eighth layer of the eight layer substrate → the second layer → the first layer)
･ The layer immediately under the wiring of RGMII is the power supply layer.
From the above, I speculated that the cause of the Ping communication failure mentioned above is "RGMII is unstable".
Also, we found that bit 2 (XGMII_ERR_INT) of register 0x0013 is "1".
* Even if 0x0013 is read, it will not be cleared.
I recognize that "This bit is 1" = "RGMII communication failure", but is not it wrong?
Could you tell me what is the cause of this bit becoming "1"?
Thank you.
