DS110DF111: DS110DF111 as a limiting amplifier in “LIMITING MODULE RECEIVER COMPLIANCE TESTS”

ANIKET

Part Number: DS110DF111

Hi,

We want to use DS110DF111 as a limiting amplifier in “LIMITING MODULE RECEIVER COMPLIANCE TESTS” in SFF-8431 Section D 1.2 along with Keysight BERT.

For that, Keysight has suggested us to do following:

use the eval board in SMBus Slave Mode.
set the bit[5] in register 0x09 (to allow the user to override retimed data) and Bits[7:5] in register 0x1E should be 000'b to select raw data.

Can you please confirm if the above configuration will make the eval board to act as the limiting amplifier.

Because in our tests, even after setting the board as above, the CDR is still ON.

over 7 years ago

0 Lee Sledjeski over 7 years ago

TI__Mastermind 43795 points

Hi,

I recommend to keep the CDR locked. The output of the DS110DF111 is a limiting amplifier either way.

Regards,

Lee

0 ANIKET over 7 years ago in reply to Lee Sledjeski

TI__Prodigy 340 points

hi,

your reply says that the output will be limiting amplifier when if CDR is ON. I reckon it means to say that the output won’t be retimed even if CDR is ON?

But from our measurements, we have seen that the signal is getting retimed. As you can see below, the ISI is cleaned up at output.

Input to TI board:

Output from TI board:

0 Lee Sledjeski over 7 years ago in reply to ANIKET

TI__Mastermind 43795 points

Hi,

To output the non-retimed data instead of the retimed data the Keysight information is correct.

Write Channel Register 0x09 = 20'h

Write Channel Register 0x1E = 01'h

Note: The CDR will still be locked, but the output will be taken after the CTLE / DFE have optimized the input prior to the CDR. Depending on how you have the scope triggered, you may be able to observe a shift in the output phase going between "Raw" and "Retimed" output modes.

Regards,

Lee

0 Muneeb Majid over 7 years ago in reply to Lee Sledjeski

Prodigy 100 points

Hi,

Even though we write the registers correctly and enable the Raw data out from eval card GUI, we see the output is re-timed or cleaned very well.

Please note that we have made the CTLE/DFE=0 and still the output is as clean as re-timed.

Besides, we tried injecting PJ of 50mUI and that too was cleaned on the raw data output.

Please refer to attached waveforms from your reference

1. Input_fromBERT_with_ISI.JPG - signal to the input of the redriver with ISI injected from BERT

2. output-from_eval_board.JPG - corresponding raw data output of input signal.

We have Remote desktop access to the retimer gui. So for the faster solution, we can set up a webex meeting.

The issue probably seems related to register setting or setting SMBus Slave mode correctly.

0 Lee Sledjeski over 7 years ago in reply to Muneeb Majid

TI__Mastermind 43795 points

I am traveling this week. A webex may be difficult today or tomorrow. Can you send me a register dump in the meantime so I can look deeper into the reason.

Regards,

Lee

0 Muneeb Majid over 7 years ago in reply to Lee Sledjeski

Prodigy 100 points

Hi Lee,

Attcahed is the register dump.

ti_regiters.cfg

(Not sure if the link works properly for cfg file. I will send it to Aniket too. He can send me in email.)

There is slight difference between the raw and retimed output. Not as much as we expect.

1. Input with ISI.

2. Raw Data output

3. Retimed Output:

Regarding the PJ, sorry had written wrongly earlier. I

If the raw data is ON, PJ is able to pass through. Only that it is somehow cleaning the ISI.

Thanks

0 Lee Sledjeski over 7 years ago in reply to Muneeb Majid

TI__Mastermind 43795 points

The extra ISI is getting picked up by the CTLE function. The register 0x52 shows a value of 50'h, this is a gain of ~ 12dB @ 5GHz
Regards,
Lee

0 Muneeb Majid over 7 years ago in reply to Lee Sledjeski

Prodigy 100 points

Oh. In the GUI, it never showed up.

We will set the 0x52 to 0'h and try again.

Thanks

Muneeb.

0 Lee Sledjeski over 7 years ago in reply to Muneeb Majid

TI__Mastermind 43795 points

Hi Muneeb,

To override the setting you cannot just write into register 0x52.

1. write register 0x2D = 88'h /* enables override

2. write register 0x03 = equalization value desired. I would look at the following values for 0x03 = 00'h, 40'h, 80'h, and 50'h. These are the first four settings in the CTLE adapt table.

Regards,

Lee

0 Muneeb Majid over 7 years ago in reply to Lee Sledjeski

Prodigy 100 points

Hi Lee,

We tried out the different settings, and attached are results.

scope.zip

Input from BERT:

Output from retimer (with 0x03=00'h):

We are getting a somewhat desired signal now. But the some of ISI is still cleaned with 0x03=00'h.

Regards,

Muneeb

0 Lee Sledjeski over 7 years ago in reply to Muneeb Majid

TI__Mastermind 43795 points

Hi Muneeb,

Even with CTLE = 00'h there is approximately 4-5 dB of gain within the linear equalization (CTLE) circuit.

Regards,
Lee

0 Muneeb Majid over 7 years ago in reply to Lee Sledjeski

Prodigy 100 points

Hi Lee,

Is there any way we can set the equalization to 0dB?

Besides, we noticed, that if we toggle the data input to retimer (Turn OFF and ON), the output of the retimer changes. Only after restarting the retimer and writing the registers again, we get back the initial output. Any idea why this is happening? The similar thing happens if the eye opening at the input of the retimer is reduced (to say 30mV).

Thanks,

Muneeb.

0 Lee Sledjeski over 7 years ago in reply to Muneeb Majid

TI__Mastermind 43795 points

Hi Muneeb,

There is no way to set the equalization to 0 dB. You can set the DWDM bit in register 0x13 (Write 0x13 = 92'h) to minimize the EQ, but it will still be ~ 2 dB at 5 GHz.

I am not exactly sure what is changing while you cycle the data input On/Off. In some cases the way the waveform starts back up can influence any adaption or locking that takes place. If you do register dumps of the original (first waveform at power-on) and post data cycle waveform I can try to explain any differences.

I'm not sure about the input eye opening either. It will depend on how the DS110DF111 is configured at the time the eye opening changes.

Regards,

Lee

0 Nasser Mohammadi over 7 years ago in reply to Muneeb Majid

TI__Guru* 93570 points

Hi Muneeb,

There could be some residual gain that is cleaning up some of the ISI that you see.

As noted by Lee, please try setting reg 0x03 to 0x40, 0x80, or 0x50. Do you see any change in your output waveform?

Regards,,nasser

0 Muneeb Majid over 7 years ago in reply to Lee Sledjeski

Prodigy 100 points

Hi Lee,

Attached are the dumps. 1. before and 2. after turning Data OFF and ON

/cfs-file/__key/communityserver-discussions-components-files/138/1134.ti_5F00_regiters_5F00_before.cfg

Reister dump after toggling the Data input:

/cfs-file/__key/communityserver-discussions-components-files/138/2477.ti_5F00_regiters_5F00_after_5F00_toggle.cfg

JItter before toggling:

Jitter after toggling:

As you can see the eye opens up.

Regarding the EQ, if we set {0x2D = 88'h ,0x03'h=00'h and 0x13 = 92'h}, will EQ be fixed to ~ 2 dB at 5 GHz, or it will adapt within 2dB?

0 Muneeb Majid over 7 years ago in reply to Nasser Mohammadi

Prodigy 100 points

Hi Nasser,

I shared them earlier.

/cfs-file/__key/communityserver-discussions-components-files/138/7345.0020.scope.zip

00'h gives the least equalization, but still cleans up some jitter. As confirmed by Lee, 00'h will still give 4-5 dB of gain.

Thanks.

0 Lee Sledjeski over 7 years ago in reply to Muneeb Majid

TI__Mastermind 43795 points

Hi,

The EQ should be fixed at ~ 2dB.

I do not see any changes in the register files.

I will have to replicate the setup to try to reporduce the effect.

Regards,

Lee

0 Lee Sledjeski over 7 years ago in reply to Lee Sledjeski

TI__Mastermind 43795 points

Hi Muneeb,

I could not replicate your results, my retimer setup will continue to display the non-retimed waveform in your post. I did look through the registers and could not find any other clues about your second cleaner waveform from post data toggle off/on.

Regards,

Lee

0 Muneeb Majid over 7 years ago in reply to Lee Sledjeski

Prodigy 100 points

Hi Lee,

That's strange. Could it be specific to our board? We will check with Aniket if he can give us another board to try with.

In meantime, anything you can suggest to us to try out to debug this issue?

Thanks.

0 Lee Sledjeski over 7 years ago in reply to Muneeb Majid

TI__Mastermind 43795 points

The only difference was that I had programmed registers 0x60-0x64 with values specific to 10.3125 Gbps

0x60 = 90'h, 0x61 = B3'h, 0x62 = 90'h, 0x63 = B3'h, 0x64 = FF'h