DS90UB913A-Q1: DS90UB913A-Q1 sequence for BIST

Hi Team,

One of our customer is using DS90UB913A-Q1 Serializer and DS90UB914A-Q1 Deserializer in DMS design and following below sequence to do BIST.

Note: BISTEN pins of both the ICs are tied to GND in the schematics.

PDB Reset

1.       Configure clock source and disable BIST through registers

a.       Enable BIST configured through register by clearing bit3 in deserializer register 0x24

b.       Enable 75MHz clock source by setting bit1 in deserializer register 0x24.

c.       Wait a minimum of 1,000ms to relock after clock source change.

d.       Disable BIST by clearing bit0 in deserializer register 0x24.

e.       Wait a minimum of 30ms to regain LOCK

f.        If LOCK is not regained the link has faulted.

g.       Pulse DESER_PBD low for a minimum of 30ms.

h.       Wait a minimum of 30ms regain LOCK.

i.         If LOCK is not regained the link has faulted.

SerDes Register Configuration

2.       Configure the Deserializer

a.       Implement Digital Reset 1 in the deserializer by setting bit1 in register 0x01.

b.       Wait 30ms to regain LOCK.

c.       Select external PCLK by writing 0b00 to bit2 and bit1 in register 0x24.

d.       Configure the registers as shown in the Table 10.                

e.       OR register 0x05 with 0xC0 to enable LF Gain.

Please share your comments on this and suggest required modifications.

Thanks in advance for your help and support.

Regards, Shinu Mathew.