DS100BR111: Determining the registers required to write to configure an EEPROM Hex file Configured for 10G-KR

Hi Lee,

It does have to do with the I2C address and the EEPROM memory location.  Please modify the first line of EEPROM data as follows.  This updated EEPROM data shifts the expect I2C addresses to match the system configuration of 0xB2 - 0xB8.

:20000000630010000000003300005800007D0000A2000000000000000000000000000000C3

Regards,

Lee

Hi Lee,

Ok that makes sense. Then, the offset of the device address map header and data is what controls which I2C address is being accessed if I am understanding that correctly.

That solves the I2C address loading issue, do you have any recommendations as to how to determine the effect of the various reserved registers on the function of the DS100BR111?

From testing, it seems for example that if I write the "default" value of register 0x2C to the value 0x2F, and register 2E to the value 0x02. This change will prevent the DS100BR111 from functioning and allowing my setup to preform link training. These registers are reserved with these default values. When preparing the EEPROM image, how am I to know which registers require their "default" and which require zero values or different non-zero values?

Would it be possible to get a full EEPROM configuration designed correctly for 10G-KR?

Regards,

Lee

Please see previous reply.

Hi Lee,

Are you using our GUI to develop you EEPROM code or doing it manually?  The Sigcon Architect information is located here.

www.ti.com/.../SIGCONARCHITECT

As a starting point I would use minimum EQ, minimum DEM and 1V VOD with a non-limiting output style.

The "default" settings are way too much equalization.

Regards,

Lee

Hi Lee,

Yes I am using the GUI to develop the EEPROM image.

Regarding the starting point, please see attached config file for the register settings which have been used to configure the EEPROM File.

Config_File.cfg

Regards,

Lee

Hi Lee,

To update my previous comment, a number of changes were made and I have observed some improvements in the link training.

1. We have created a new EEPROM using the SigCon tool and have adjusted the VOD, DEM and BOOST settings to the optimal values based on trial and error rate reported by the end devices. Our current working EEPROM is attached below. Even with the optimization we still have significant number of errors reported by the end devices 50%+ error rate. Do you have any further suggestions of improvements or mistakes that exist in this EEPROM?

Baseline_Functioning_EEPROM.cfg

2. One bit that we believe should be set based on the datasheet is register 0x08 bit [3] since our implementation is >8Gbps. When we set this bit the error rate goes to 100%. Do you have any additional information as to what this bit does? Is there any specific reason why it would cause our "partially working" configuration to completely stop? When looking into the example 10G-KR configuration provided (datasheet table 12), it is seen that register 0x08 is set with a value of 0x04 and not with what I would expect to see of 0x0C based on documentation in a 10G-KR example sequence.

3. Are there any tools for the DS100BR111 that can help speed along this process? Schmoo capabilities etc...?

Regards,

Lee

Lee,

I can help to create an EEPROM configuration that may improve your system performance.  Can you provide a diagram of the system channels on the DS100BR111 inputs and outputs with distance and loss information to help me choose appropriate settings.

Regards,

Lee

Hi Lee,

The setup which we have currently implemented, including the channel lengths and loss information can be found below.

Regards,

Lee

Hi Lee,

Running two repeaters in series presents a significant challange for 10G-KR operation with link training.  There are a lot of variables to understand and the training algorithms tend to be impacted by two DS100BR111 repeaters in series.

For 10G-KR operation you will definately need to use the non-limiting mode of operation.  This is achieved with the MODE pin or by overriding register 0x08[2] = 1 and setting 0x10[6] and 0x17[6] = 0 (this is already done).  I would try to keep the equalization on the low side to help keep the system as linear as possible.

0x08[3] is for PCIe applications and is not needed in this case

In order to make progress on this application issue,you access to the 10G-KR serdes training logs, all receiver settings, and eye monitor information will be a big help.

I would run the baseline configuration with these changes and increase the equalization settings one step at a time in an attempt to bring the SerDes Rx into its nominal range of operation.  Another option is to replace the DS100BR111 devices with DS125BR111 devices which have improved linearity and work better in 10G-KR applications.

0xF Channel 0_CH A EQ Setting 01

0x23 Channel 0_CH A VOD Control 10  (1100mV)

0x2D Channel 1_CH B VOD Control B1  (1100mV)

Which side of the DS100BR111 devices has your equalization setting = 0x06?  The cable side or the SerDes side?

Regards,

Lee