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Linux/DP83867IR: DP83867IR Ethernet PHY and FPGA

Yiping Wang66
Prodigy 50 points
Part Number: DP83867IR
Other Parts Discussed in Thread: MIO

Tool/software: Linux

I have a question about using two ethernet PHY chip DP83867IRPAPT interface with Zynq7010 MIO PS interface. I have first PHY without Address strap so it address is by defualt 00000(b), the 2nd PHY with strap mode2 on RX_D4, so this PHY's address should be 10000(b) by design. The problem is that when running software, zynq7010 always get the address to be 01111(b) and 11111(b) respectively. It looks like the address strap does not work OR distorted. Does anybody  has answer about this issue? Thanks.

Ping

P.E.

  • 0
    TI__Mastermind 18425 points
    Hi,

    The Lower 4 bits of the PHY address are controlled by RX_D0 and RX_D2. It looks like they are being pulled into mode 4 which is causing all 4 lower bits to be '1' instead of '0'. Can you check if there are internal pull up resistors in the Zynq7010 or if the Zynq7010 is driving voltage on the RX_D0 and RX_D2 pins during power up?

    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Prodigy 50 points

    Yes, your comment helps me. Finally I have found the problems is that the sync7010 we use has weak pull-up on all its MIO ( which is our Ethernet PHY interface pins). This pull-up contributes to our wrong power-on reset (POR) strap address of the PHY. The solution is right after POR, re-configure the all interfaced IO configure registers on Zynq to be High-Z state and then reset the Ethernet PHY. In this case you need to have you Ethernet PHY reset to be controlled by Zynq, not you system POR.

    Thank you very much

    Ping