DP83822I: max. allowed clock input jitter

Gerald Pichler

Prodigy 40 points

Part Number: DP83822I

The datasheet shows only a typ. Clk-to-Clk jitter. What is the max. number for the Jitter?

over 7 years ago

0 Geet Modi over 7 years ago

TI__Mastermind 26320 points

Hi,

I believe you are referring to 25Mhz input Oscillator specifications defined in Table 13.4. as:

cycle to cycle jitter need is : 50 psec
Long Term jitter need is : max 1 nsec.

Not sure If I am missing something here.

Regards,
Geet

0 Gerald Pichler over 7 years ago in reply to Geet Modi

Prodigy 40 points

I'm using a 50MHz Oscillator but the numbers vor the Jitter are identically. The 50ps are typical. What is the max. tolerance for the jitter?

0 Geet Modi over 7 years ago in reply to Gerald Pichler

TI__Mastermind 26320 points

Hi,

I have responded over the email. Closing this thread.

Regards,
Geet

0 Gerald Pichler over 7 years ago in reply to Geet Modi

Prodigy 40 points

I got no email.

Can you post the data in the forum? This could also interesting for other users...

0 Geet Modi over 7 years ago in reply to Gerald Pichler

TI__Mastermind 26320 points

Hi Gerald,

I have forwarded information to TI FAE supporting you.

Jitter of input clock has direct correlation to Transmitter jitter. Max shall be looked from IEEE Transmitter jitter requirement which is 1.4ns for 100BaseT.

Regards,
Geet

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DP83822I: max. allowed clock input jitter