DP83867CR: Tx/Rx Delays and Tx FIFO Depth

Russell Wetherley1

Part Number: DP83867CR

Hello E2E,

Quick questions on the 83867.

RGMII TX/RX delay - Are these registers strictly for length compensation? Any reason we shouldn't set these to the minimum if the bus is matched?

TX FIFO Depth - Can we get an explanation of this or can you point out where it is explained in the datasheet?

Thanks for the help!

Regards,

Russell

over 7 years ago

0 Ross Pimentel over 7 years ago

TI__Mastermind 23675 points

Hi Russell,

If your RX data lines are matched to your RX_CLK, you must implement internal delay either in the PHY or MAC.
Same goes for TX path. If there is no delay, all edges are aligned and you will not have sufficient setup time.

FIFO depth is in regards to the offset from the line driver clock to the local reference clock.
Without a FIFO, you can overflow the path since the two clocks are not synchronized.

0 Russell Wetherley1 over 7 years ago in reply to Ross Pimentel

TI__Expert 4255 points

Thanks Ross the boss!

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DP83867CR: Tx/Rx Delays and Tx FIFO Depth