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SN65DSI85: Image not displayed on the display with the data streamed from MIPI

Rangarajan Krishnamachari
Intellectual 280 points
Part Number: SN65DSI85

Hello,

I have an ELECS system driving the MIPI data to the TI IC SN65DSI85 EVM kit and to the LVDS display, and I am able to display the test pattern using the TI test pattern generator. I try to display the image sent from the MIPI generator and I do not see anything displayed on the image, the following is the CSR register read and it shows the PLL is locked and I  am setting the LVDS clk to 495MHz and using a clk divider vsalue of 5 to generate my LVDS clk. Any insights to resolving this issue will be helpful.

Thanks
Ranga

  • 0
    Intellectual 280 points

    DSI Tuner data for CSR registers attached above.

  • 0 in reply to Rangarajan Krishnamachari
    TI__Mastermind 35130 points

    Hello Ranga,

    Your post is a little bit confusing. You said you are setting the LVDS clk to 495MHz and using a clk divider of 5 to generate your LVDS clk. Do you mean that you're using a DSI clk frequency of 495MHz, and using a clk divider of 5 to generate the 99MHz LVDS clk? But then neither this or your description match up with your screenshot for the DSI Tuner.

    Please try the attached txt file for the CSR settings that I generated with the tool. You can also see the parameters I input by importing the attached .dsi file into the DSI tuner tool:

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/Ranga.dsi

    Fullscreen Ranga.txt Download 
    //=====================================================================
// Filename   : Ranga.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x07
0x0B              0x20
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x63
0x13              0x00
0x18              0x7a
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0x00
0x21              0x05
0x22              0x00
0x23              0x00
0x24              0x00
0x25              0x00
0x26              0x00
0x27              0x00
0x28              0x20
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x0a
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x01
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0x5a
0x35              0x00
0x36              0x00
0x37              0x00
0x38              0x00
0x39              0x00
0x3A              0x00
0x3B              0x00
0x3C              0x00
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Intellectual 280 points
    Hello I.K.,

    Thanks for the detailed info, I was able to test with your data and it worked.

    -Ranga