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TPS65986: SLEEP mode current higher than expected

Eric S
Expert 5640 points

Part Number: TPS65986

Trying to understand what might be causing higher than expected SLEEP mode current.   Datasheet spec's IVIN_3V3 of 58uA(typ), we're seeing ~260uA draw.   We've confirmed there are not additional loads on 3V3, and have checked I/O for potential leakage paths as well.  Any idea what could be causing the excess current draw?   We've been informed to confirm we're in S5 mode, where I2C is disabled, and we are working to confirm now...  is there an expectation of what the delta would be if I2C is still active, versus disabled?   (I believe that's S3 vs S5?)

  • 0
    TI__Mastermind 36756 points

    Hi Eric,

    A few things to check when seeing abnormal current consumption in sleep mode:

    - Ensure you are entering the correct sleep mode. Is the First I2C transaction lost or does the I2C remain active?

    - Check to see no GPIOs are driving devices that draw large currents. (This current will be added to our IC's current consumption)

    - Make sure no current consuming devices are attached to LDO_3V3 (This current will also be added to our IC's current consumption)

    If this answers your question, PLEASE select This resolved my issue

    Thank you,

    Eric

  • 0 in reply to Eric Beljaars
    TI__Expert 5640 points

    Eric,  They've confirmed they are losing the first I2C transaction, so they do seem to be getting into I2C off state (S5).  However, they are still seeing higher current on 3V3 rail than expected.  (on order of 260uA instead of ~58uA-typical spec'd).   Interestingly, in another test, they applied 5V to the PP_5V0 / PP_CABLE pins of the device, but at different times, and see different current draw on 3V3 depending on when 5V0 was applied:

    1. Apply 3V3 and 5V0 simultaneously:   After boot-time, the 3V3 current is at ~260uA, and 5V0 current is at 9.4uA
    2. Apply 3V3 first, wait for boot, then apply 5V0:   After boot, 3V3 current is at ~260uA.  After applying 5V0, the 3V3 current drops to ~125uA (5V0 still at 9.4uA)

    This is also totally repeatable, and really doesn't make sense since 5V0 is being applied to the PP_5V0 pins, not VBUS (so LDO_3V3 and internals are still powered from 3V3 input, not from VBUS).   The 9.4uA on 5V0 appears to be normal leakage, I think the spec says a "max" of 100uA leakage on PP_5V0...  the question is why applying 5V0 to these pins affects SLEEP current at all.

    Questions:

    • Does this information help point to anything you can think of for them to check?
    • Why would SLEEP current drop by ~130uA when they apply 5V0 to the PP_5V0  pins?
    • Even then, we're still trying to understand why the SLEEP current is still more than double the specified typical value of 58uA?
    • Is there any chance they're in a "relaxed" but not "OFF" I2C state or something?  TRM mentions an "S4" state in Table 1-1 (Page-8), but I don't know what that would correspond to in this device, particularly since this is not an option in the Configuration tool.
  • 0 in reply to Eric S
    TI__Mastermind 36756 points
    Hi Eric,

    This doesn't really indicate what could be drawing current in their system. It would be very helpful if you could find where this current is going in their system. It would typically be leaving the TPS65986 on either LDO_3V3, one of the GPIO pins, or potentially even the SPI pins. Based on the configuration settings you described, they are indeed entering S5 state. Can you check to see where the current is flowing out of the TPS65986?

    Thank you,
    Eric