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UCC21520: Creepage distance

Part Number: UCC21520


Hello everyone,

I am designing a half-bridge using UCC21520 to drive the FETs and I am a bit concerned about the creepage distance on the isolated side. For now the DC bus voltage will not exceed 500 Volts or so, but the end application may see up to 1kV DC. I can manage the distance between the traces but pins 11 and 14 seem awful close to one another (< 100 mils). Assuming the PWA is conformal coated after assembly, is this distance sufficient.

I am also attaching a picture of the prototype layout that will not be conformal coated (unless necessary), but will be used at a lower voltage (up to 500 VDC). Any recommendations and insights are appreciated!

Thanks,

Saurabh

  • Hello Saurabh,

    I am an applications engineer supporting UCC21520. Sufficient creepage and clearance distance is determined by the high voltage standard you are trying to meet. For example, UL 796 indicates functional isolation requirements of around 40V/mil for a clean board at ~85% humidity; UCC21520 has a worst case clearance of approximately 90 mils (3x pin spacing of 1.27mm - 3x pin width maximum of 0.51mm), which is theoretically functionally isolated up to about 3600V. If the end product is covered under UL 60950-1, this spacing is fine even uncoated, assuming the end equipment remains clean and at an acceptable humidity to avoid condensation. On the other hand, if the product must meet a more stringent standard such as IPC2221B, a conformal coated board can reasonably reach about 985V with the same worst case spacing.

    From a purely physics standpoint, the distance in this layout as pictured is sufficient for a working voltage of 500V, as long as the board is kept clean and free of condensation. We have tested uncoated layouts with similar spacing in our lab up to 800V with no issues. If you have a specific standard you are trying to meet, the standard document should include a method for calculating the required spacing.

    Regards,