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DS90UB947-Q1: Communication between ds90ub947 and ds90ub948

Zhiguo Li
Prodigy 30 points
Part Number: DS90UB947-Q1

Hi  Ti

        At the beginning of board turn on,CPU will send a high level signal from GPIO0 of DS90UB947 to GPIO0 of DS90UB948,Then initialize CPU LVDS driver.but we can see an expected low level signal at the DS90UB948 side,lasted several milliseconds,meanwhile the FPDLINK signal works abnormal too,I wonder if it is related to PCLK changing from internal oscillator to LVDS clock.please help to anaylise this problem,thanks.

     

  • 0
    TI__Mastermind 30515 points
    dependent on the input conditions, UB947 can detect the PCLK availability after power-on, if NO PCLK is detected, the internal clock would be used. after PCLK is stable, UB947 will change the internal clock to external clock and the output has changed meanwhile.
    for your case, it could be. for details, you can capture the signals for further analysis.

    Steven