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DS92LV18: Relation about PLL lock and DIN signal

Satoshi
Guru 19675 points

Part Number: DS92LV18
Other Parts Discussed in Thread: DS92LV16

One customer is using DS92LV18, but one problem is below. 

At first DIN17 ～ DIN00 is set all "1" for power up timing and PLL locked, but DIN17 ～ DIN00 is change to "111001000111111111", PLL was loses lock.

Please let me know about three points below about relation for lock and DINx;

①Is there any influence for lock or loses lock by array of data: DIN17～DIN00? 

②Is there lock condition for array of data?

③If there technical document near snla201(for DS92LV16, attached below), please let me know.

Additional information;

・TPWDN: High, RPWDN: High, SYNC: Low

・Signal rate: 600Mbps (30MHz × 20bit)

・Cable length: 1000mm (LVDS twisted pair) 

Best regards,

Satoshi

  • 0
    TI__Genius 10250 points
    Hello,

    The deserializer lock is affected by the data initially. The data has to be random (or SYNC patterns) until lock is achieved. Once it locks it is not affected by the data anymore. The loss of lock normally happens if there are errors in the clock info (start and stop bits). Once lock is lost, then again the data has to be random or SYNC to achieve lock again. The info in snla201 is mostly applicable to DS92LV18 too.

    Regards,
    Yaser