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DP83867E: SGMII LVDS and Mirror mode on DP83867E

Shaun Viola
Prodigy 20 points
Part Number: DP83867E

Hi, 

I'm using the DP83867E to convert from ethernet to SGMII LVDS. I have the evaluation board and measured output signal from SOP. I noticed there was no DC bias on the signal and was wondering why this is the case and how it is achieved given SGMII LVDS spec is supposed to have an offset voltage. Additionally, I have a question about the RJ45 mirror mode,  the data sheet states "In some multiport applications, RJ-45 ports may be mirrored relative to one another." is there a specific example of when this is required? I want to use the chip to go from one ethernet port to another via an optical link, does it matter if I enable mirror mode or not? the EVM has worked over the link and mirror mode is enabled on this so I'll stick to this configuration for now but I just want to better understand mirror mode.

Thanks,

Shaun

  • 0
    TI__Mastermind 19780 points
    Hi Shaun,

    Mirror mode reorders the output pins of the RJ45. It is a convenience feature to keep you from changing layers with your MDI if you do not want to. Please see this E2E post on how pins are reordered in mirror mode.

    e2e.ti.com/.../544013

    We require AC coupling of the SGMII output to an LVDS receiver, as SGMII is DC balanced this is OK, and this should be acceptable for any LVDS receiver you have. You must not DC couple the LVDS receiver to a DP83867. This is industry standard for Ethernet SGMII links between MAC and PHY. Because of this, you may need to bias the LVDS receiver in accordance with that device's needs.

    Best Regards,