This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DP159: Register information (Not X-Mode)

Guru 19785 points
Part Number: SN65DP159

Hi Team,

Could you please tell us the information of the following registers ?

The background of this question is that customer can show video through DP159 from Xilinx evaluation board, however, cannot show video using their own board.

ADDR   :   Data (Pass)     Data (Failed)
0x25     :      0x80               0x80
0x27     :      0x70               0xF0
0x2A     :      0x01               0x00
0x2C     :      0x02               0x00
0x2D     :      0x09               0x00

There were register value differentiation in above registers. They would like to know what they show to understand the symptom.

Thanks in advance,

Best Regards,

Kawai

  • Kawai,

    Apologies, we have no defined values for those registers. Are there any other differences?

    Regards,
    JMMN
  • Hi JMMN-san,

    There were following differences in the disclosed registers.

    0x17[4] : TST_INTQ[0] 0 -> 1
    0x1A[2] : BERT_CNT[14] 1 -> 0
    0x1C + 0x1D : BERT_CNT[35:24] 0x0902 -> 0x0000
    0x20[7:4] : Reserved 0x1 -> 0xF

    Best Regards,
    Kawai
  • Hi Kawai,

    Was any eye scan or debug testing run before reading back registers? Otherwise, these registers don't have any meaning in normal operation.

    Regards,
    JMMN
  • Hi JMMN-san,

    Customer might had tried to debug using EyeScan Tool.

    Could you please confirm following register data. This is the register information when it fails.
    Please advise us what they could do to solve the problem.

    ADDR: +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
    0000: 44 50 31 35 39 20 20 20 01 06 31 80 48 00 00 0F
    0010: 00 00 00 00 00 80 00 F0 00 00 00 00 00 00 00 00
    0020: F0 15 02 00 80 4A 00 00 A4 9F 01 00 00 F8 D9 08

    Best Regards,
    Kawai
  • Hi Kawai,

    What data rate traffic are they sending when the registers have these values?  If they are using I2C mode, they need to configure tx_terms in Register 0Bh.

    Regards,

    JMMN

  • Hi JMMN-san,

    Thanks for pointing out.

    I think it was better to have the same automatic mode in I2C mode or to have override bit to enable Pin setting or register setting.

    Best Regards,
    Kawai