SN75DP130: SN75DP130 Package Model

We are currently looking into this issue and will get back to you as soon as possible.

KT

You are correct that there is no existing package model. If you take a look at the simulation example (ADS) in user’s guide, it doesn’t show the package model either. I believe the user guide made an erroneous reference to the package model, and needs to be updated to remove this reference.

Thanks
David

Hi David,

Thanks for update. Could you please provide the package model ? We are not seeing good correlation between lab and simulation (for TDR waveform at SN75DP130 location and eye diagram). When I manually add parasitic capacitance to sim to make the sim match the lab TDR impedance dip observed at SN75DP130, then I observe much better sim correlation to lab. However, I really need the package model to gain confidence that the PCB changes planned will fix the DisplayPort compliance problem observed in the lab.   

Regards,

KT

KT

What DisplayPort compliance problem are you seeing in the lab? If you can send me layout file and give me a description of the problem, I can take a look at it and provide some suggestions.

Unfortunately, the SN75DP130 was released several years ago and we no longer have the people that can support the model request.

Thanks
David

Hi David,

We observe several failures of the Test 3.3 PreEmp, 0dB at 1.62G and 2.7G due to inflections observed in signal after transitions. I can send you the layout file and report if you contact me at my email address for this account.

KT

KT

I send you a friendship request, would you please send me the layout file after you accept the request?

Thanks
David

Hi David,

Gerbers and Allegro layout sent.

KT

KT

Is U14 DP130? If so, the two issues I am seeing are:

1. The thermal pad did not follow DP130 datasheet recommendation
2. And when using ground guard around high speed trace, you want to rout them end to end so you have consistent reference, otherwise there will impedance variation between the portion of trace having ground reference and the portion of trace that does not have ground reference.

What is your EQ level and Pre-emphasis level? Since you are running at 1.6 and 2.7G, have you tried to set both of them to 0?

Thanks
David

Hi David,

Yes U14 is DP130. 

1. Ok, we will review and modify thermal pad.

2. Ok, we will improve trace symmetry.

3. The DP130 EQ is set for 0 dB via I2C. The DP PHY Tx test that is failing is Test 3.3 "Pre-Emphasis Level Verification and Maximum Pk-Pk Differential Voltage Testing (Normative)" for 0 dB level tests, so the DP130 pre-emphasis is set to 0 dB via AUX CH snooping. The test fails because consecutive identical bits must have swing within 0.25 dB of each other, but a ripple in the waveform causes the test to fail. Appears to be reflection issue based on testing with serial data analyzer and TDR: modifying the impedance on the board by placing finger over components or traces modifies waveform ripple and allows test to pass. The largest impedance variation (dip) observed by TDR is at DP130. Is there a known output impedance (output return loss) limitation with DP130 ? 

4. I will try to send you DP test report (42MB) or portion of it if transfer size is limited.

KT

Hi David,

DP Tx test report has been sent to you. For Test 3.3 "PreEmp, 0dB", there are five test failures. The waveforms shows bump/ripple that is causing the test failures. The bump/ripple can be seen in Test 3.3 for 1.62G, 2.7G, and 5.4G rates, but due to the position of the reflection and test method it only causes test failures in 1.62 and 2.7G tests. The bump/ripple can also be seen in the 1.62G and 2.7G eye diagrams.

Regards,
KT

KT

Output impedance nominal is 50ohm. PCB differential characteristic impedance is 76.4ohm min, 107.6ohm max, and 92ohm typical.

Are you seeing the failure across all four lanes? And is link training enabled or disabled for the test? If link training is enabled, would you please disable the link training and repeat the test?

Have you tested multiple boards and is the result consistent across them?

Thanks
David

Hi David,

1. Re: "76.4ohm min, 107.6ohm max, and 92ohm typical."

What is this referring to ? Is this the DP130 EVB TDR measurements ? DP130 board design recommendations ? 

2. Yes, failure is observed across 4 lanes.

3. Our product/DUT enters compliance test mode by reading the DPCD registers of the DPR-100 AUX CH controller. Our product fully supports test automation using the DPR-100, so for these 3.3 tests each swing and emphasis setting is exercised. Our console logs report the swing/emphasis setting used and we can observe AUX CH messages with DPA-400 AUX CH analyzer. Does this answer your question with regards to link training ? 

4. Yes, this failure occurs across multiple boards, with only small variation in results.

Regards,
KT

KT

The PCB impedance requirement is part of DisplayPort specification.

I noticed you are using 0.1uF AC coupling capacitors, have you tried to change the capacitance from 0.1uF to 0.22uF? This will help slowing down the slew rate of the signal and reduce the reflection.

Thanks
David

Hi David, 

1. The nominal 92 ohm PCB differential impedance appears to be only for FAUX channel in DP1.2, which is now a deprecated feature. Main link impedance is nominal 100 Ohm differential. Did TI target 92 Ohm for the DP130 EVB for the main link diff pairs ? 

2. I have not tried changing the 0.1uF caps to 0.22uF on the actual board. I just tried the change in HyperLynx simulation and it does not improve the bump, however I will try on actual board to confirm. 

Regards,

KT

KT

Yes, you are right, that is only for FAUX. For DP130, we still targeted 100ohm differential.

Thanks
David

Hi David,
Would you be able to send the DP130 EVB layout gerbers ?
Regards,
KT

Hi David,
File received, thank you.
KT

Responding to automated email regarding resolved or not resolved status: For the original request in regards to missing package model for SN75DP130, TI responded that package model is not available even though documentation states that it is. Exclusion of package model in IBIS-AMI simulations limits the simulation accuracy and correlation. For that reason, the issue is not resolved, but since TI has stated that it cannot be provided then I suppose this thread can be closed. Not resolved. I will enter DisplayPort Test 3.3 failures as separate thread.