TLK10034: PLL multiplier setting

Hello,

In TLK10034 datasheet, table 3-1 says that the SERDES PLL multiplier for 10GBaseKR is 16.5x when the reference clock frequency is 156.25MHz. In table 7-4 the bits corresponding to 16.5x is given as "1100". The default value of the corresponding bits in the register (1E.0x0002 [3:0]) is"1101" which according to table 7-4 corresponds to PLL multiplier 20x. We are using the HS side of TLK to interface with DS100MB203. With the default setting of the register, the 10G link is coming up. But when we change the register setting to 16.5x (that is 1E.0x0002. [3:0]) TO “1100”, the link goes down. Why is it so? Is the datasheet information correct?

Thanks,

Ashitha