Hi TI,
my project is utilizing the XIO2001 and we are in layout phase of the project. For recommended layout guidelines for the chip, the CLKOUT signals are recommended to be 'slightly' longer than the longest synchronous PCI bus trace in the datasheet. I Can I get any quantification to 'slightly' longer in terms of lengths or propagation time? I understand the theory; ensuring that the data lines have changed and settled at their given value before the next rising clock edge, but can I figure out what that length increase actually is for my PCB designer?
Thanks!
Jesse
