SN65DSI83-Q1: Is this part - or the 84 or the 85 - compatible with the DSI interface from a Raspberry Pi - DSI clock input characteristics

Thank you for your rapid response, however there is work by Eric Anholt (who is a contributor to the Rasbperry Pi O/S dev team) which gets us past the official "it's impossible, don't ask" view,

https://github.com/anholt/linux/wiki/Raspberry-Pi-and-other-MIPI-DSI-display-panels

Also, the current kernel sources now contain DSI drivers for several [native DSI] panels, so I'm not going to give up hope just yet.

I have found empirically that adding a 2.0k resistor from each DSI clock pin to Vcore brought the average DC voltage on the clock pins up to about 270mV, very comparable with what is seen when the bus is connected to the official display

The status register (0xe5) now shows the PLL is locked,  and I get an LVDS clock output which is smack on the expected frequency when divided by the divisor register. 

I am still seeing occasional sync errors, but I feel I am getting close.  

I will post again for the benefit of others if I finally succeed.

OK - after a great deal of experimentation, I eventually concluded that the  only thing wrong related to sync information.

Using the DSI Tuner, I established register settings which produce a partial picture, but bizzrely, this is with register 0x10 set to 0x3e as recommended by the Tuner (from the datasheet, I'd set a value of 0x18)

The datasheet says that the top three bits are "reserved and should not be written" - well, one has to write SOMETHING, and I'd arbitarily chosen to set bits 7:5 at zero.

However, the Tuner knows better, and as soon as I set that 0x20 bit in that register - BOOM! the LVDS outputs lit up.  That bit is described as "DSI Mode" in the Tuner (and simply 'reserved' in the datasheet

I now have to work out why I have only half the panel lit up bit it is a start.

It is almost as though the chip is expecting two lanes of data, even though I have only told it there is one.

I shall continue to tinker.  I think this has proved, though, that in principle, these TI chips can display pictures from the R-Pi's DSI port - profound relief here from the UK!

AA070ME01_Datasheet.pdfFirstly, many thanks for your response - it is much appreciated.

I attach the datasheet, and the .dsi file as requested.

<original post contained a red herring here - deleted by Chris to reduce confusion>

BUT - I just thought I'd experiement with these mysterious "DSI Channel Mode bits, and to my surprise and delight, when I put 0x5E in to register 0x10 - Bingo!  Full width display.

I'm sure you will have an explanation for that, but to me those 'reserved' bits don't seem as innocent as the datasheet might imply!

If you do have an explation for all this, it would doubtless be really helpful to others if you can post it - it's probably absorbed (I won't say wasted - I'm learning all the time) two days getting this last bit sorted out.

Hi Chris,

Addresses 0x00 - 0x08 say DSI85 for all three of the DSI83, DSI84, and DSI85 devices. This is probably because they have the same die. 

Those reserved bits in register 0x10 correspond to the SN65DSI85, which has a dual-channel DSI interface:

With the DSI83, 6:5 should be 0b01 to disable DSI channel B. If you write 0b10 to it then both DSI channel A and channel B are enabled as separate DSI receivers, so I can see why it would work in this mode since channel A would be independent of channel B, but it's strange why 0b01 (single channel DSI receiver) doesn't work. 

Can you try writing 0xDE and then 0xBE to register 0x10? I would like to see what effect bit 7 has.

Regards,

I.K.