Hello support team,
Our customer is using TL16C754B now.
There is a phenomenon that BIT 3 - 0 of Modem Status Register (MSR) does not work properly under the conditions of customer's usage.
In case that the time from the falling edge of CD, CTS and DSR to reading of MSR is short (eg less than 20 ns), BIT 3, 1 and 0 (ΔCD, ΔDSR and ΔCTS) can not aquire the state change of CD, CTS and DSR.
If it is over 60 ns, it seems to work normally.
BIT 7, 5 and 4 (CD, DSR and CTS) can aquire the state change of CD, CTS and DSR even if the time from the falling edge of CD, CTS and DSR to reading of MSR is short.
【Question】
(1) How much wait time is required from the falling edge of CD, CTS and DSR to reading of MSR?
(2) If the time from the falling edge of CD, CTS and DSR to reading of MSR is shorter than the value of above (1), can't MSR BIT 3, 1 and 0 (ΔCD, ΔDSR and ΔCTS) acquire the state changes of CD, CTS and DSR?
(3) We think that data storage timing of MSR and the output timing of INT are nearly equal. Is our understanding correct?
(4) If the above (3) is correct, is the circuit of TL16C754B configured so that it works such operation?
(5) We think that the above (1) is almost equal to T18d of Figure 14 on page 21 of the data sheet. And I think that it is necessary to wait for more than 70 ns. Is our understanding correct?
Sincerely,
M. Tachibana