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TL16C754B: About read timing of MSR

Masanori Tachibana
Genius 5350 points
Part Number: TL16C754B

Hello support team,

Our customer is using TL16C754B now.
There is a phenomenon that BIT 3 - 0 of Modem Status Register (MSR) does not work properly under the conditions of customer's usage.
In case that the time from the falling edge of CD, CTS and DSR to reading of MSR is short (eg less than 20 ns), BIT 3, 1 and 0 (ΔCD, ΔDSR and ΔCTS) can not aquire the state change of CD, CTS and DSR.
If it is over 60 ns, it seems to work normally.
BIT 7, 5 and 4 (CD, DSR and CTS) can aquire the state change of CD, CTS and DSR even if the time from the falling edge of CD, CTS and DSR to reading of MSR is short.


【Question】
(1) How much wait time is required from the falling edge of CD, CTS and DSR to reading of MSR?

(2) If the time from the falling edge of CD, CTS and DSR to reading of MSR is shorter than the value of above (1), can't MSR BIT 3, 1 and 0 (ΔCD, ΔDSR and ΔCTS) acquire the state changes of CD, CTS and DSR?

(3) We think that data storage timing of MSR and the output timing of INT are nearly equal. Is our understanding correct?

(4) If the above (3) is correct, is the circuit of TL16C754B configured so that it works such operation?

(5) We think that the above (1) is almost equal to T18d of Figure 14 on page 21 of the data sheet. And I think that it is necessary to wait for more than 70 ns. Is our understanding correct?

Sincerely,
M. Tachibana

  • 0
    TI__Guru 73221 points

    Hey Tachibana-San,

    "(1) How much wait time is required from the falling edge of CD, CTS and DSR to reading of MSR?"

    -Looking at the timing diagrams on page 21 (t18d) suggests the time that delta CD, delta DSR, and delta CTS should be ready in the MSR will be about 70ns. The 60ns timing you found is likely closer to the typical timing but 70ns will be a better number for you to be using.

    "(2) If the time from the falling edge of CD, CTS and DSR to reading of MSR is shorter than the value of above (1), can't MSR BIT 3, 1 and 0 (ΔCD, ΔDSR and ΔCTS) acquire the state changes of CD, CTS and DSR?"

    -I assume in this question you are asking why it isn't instantaneous. I do not have access to the internal logic of the device but I believe there is multiple blocks of logic involved in finding ΔCD, ΔDSR and ΔCTS as opposed to bits 7, 5, and 4 of MSR which only uses a NOT logic. The delta values require a D-flip flop and an edge rate to clock in the current value and clock out the new value. There is a small time delay in all this because this logic is done using FETs which have parasitic capacitance so the rise time on these gates have  some time before the FETs turn on.

    "(3) We think that data storage timing of MSR and the output timing of INT are nearly equal. Is our understanding correct?"

    -Yes, I believe both of them are based on a rising edge of baudrate clock. (D flip flop of the delta CD ect will likely be based on the rising edge)

    "(4) If the above (3) is correct, is the circuit of TL16C754B configured so that it works such operation?"

    Yes.

    "(5) We think that the above (1) is almost equal to T18d of Figure 14 on page 21 of the data sheet. And I think that it is necessary to wait for more than 70 ns. Is our understanding correct?"

    -I do not have access to the internal logic of this device as it is very old and not on our internal servers however I am in the same thinking as you here. The MSR bit 3,1, and 0 are based on a rising clock edge and have an internal delay due to gate capacitance on FETs which is likely 70 ns MAX. If you want to accurately read MSR bits 3-0 then I would suggest the customer wait atleast 70 ns before reading the internal register.

    Thanks,

    -Bobby

  • 0 in reply to BOBBY
    Genius 5350 points

    Hello Bobby-san,

    Thank you very much for your detailed explanation.
    I will ask you some additional question.

    (5) According to the data sheet, ΔCD, ΔDSR and ΔCTS are "cleared on a read".
    In case that the states of CD, CTS and DSR change during MSR is being read, can't the state change of them be acquired?
    If the MSR is being read repeatedly, can't the above their state changes be acquired even at the next MSR read timing?

    (6) If the above (5) is so, we think as follows.
    Read data is transferred from MSR register to the ports D7-D0 during the IOR period. And acquired information of the state changes of CD etc. would be cleared during the period of IOR.
    During the period of this IOR, even if the next state changes of CD etc. occur, they would not be accepted.
    Is our understanding correct?

    (7) You answered "70 ns" to questions (1) which I asked the previously .
    Does this "70 ns" depend only on the delay of FET? Or it depends on the frequency of XTAL or the external clock?
    If so, what is the frequency value in case it is 70ns?

    Sincerely,
    M. Tachibana

  • 0 in reply to Masanori Tachibana
    TI__Guru 73221 points

    Hey Tachibana-San,

    I believe this is how the logic is done for finding  ΔCD, ΔDSR and ΔCTS. (I base this off of how we typically do logic some of our other devices) This diagram does not include the logic for a read (which is set to reset the MSR bits)

    "In case that the states of CD, CTS and DSR change during MSR is being read, can't the state change of them be acquired?"

    This is something I am not sure about. To me, the state change could be lost because when the MSR is read, the data could get cleared but it depends on how the data is cleared. If the device MUXs in a zero to the MSR then, it may be possible to pull in to the missed data during the next read. I don't currently have a board I can test to verify this... This is something you can probably have the customer check I by holding IOR low and then changing the state of CD/CTS/DSR then going to read MSR after changing. If MSR bits 0-3 have changed then we know that we can still read data while CD/CTS/DSR change during a read transaction (this is what I expect to be the case).

    "Does this "70 ns" depend only on the delay of FET? Or it depends on the frequency of XTAL or the external clock?"

    -I believe this will be based on the non ideal characteristics of the FETs which make up the logic. In the diagram I drew above, I suspect the clk line on the second FF takes some time before the FET actually turns on (there needs to be enough charge on the gate to turn on the FET which the pulse has its own ramp rate) and after the clock line sees a positive voltage/edge, there will be some minor prop delay between D and Q before it makes it into the MSR register.

  • 0 in reply to BOBBY
    Genius 5350 points

    Hi Bobby-san,

    Thank you for your kind response.
    Your opinion was very helpful.

    According to our customers confirmation, in case that t18d is short time (eg 20 ns), ΔCD, ΔDSR and ΔCTS are not output. So , I think it might be impossible to acquire the state change of CD, DSR, CTS during MSR is being read

    If there is something that is not understood for additional, I will ask again.

    Thank you very much.
    Best regards,
    M. Tachibana