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DS90UB913A-Q1: CML output frequency isn't synchronized with PCLK

K.Yaita
Guru 29720 points
Part Number: DS90UB913A-Q1
Other Parts Discussed in Thread: DS90UB913A-CXEVM, , DS90UB914A-CXEVM

Hi Team,

I am evaluating DS90UB913A-CXEVM itself (not connected to Deserializer) and confirmed CML output frequency isn't synchronized with PCLK pin that is connected from pulse generator.
It seems fixed 50MHz internal oscillator is used in this case.
Is it expected behavior?
If the answer is yes, how to synchronize CML output with PCLK pin?

The background of the question is my customer considers to evaluate output waveform quality of his system in PCLK mode without connecting Deserializer.

Best Regards,
Yaita / Japan disty

  • 0
    TI__Genius 10475 points
    Yaita-san,
    If there is no PCLK provided when the device is powered up, the serializer will operate at its internal default oscillator frequency. When the PCLK is provided or starts again the device will switch from the internal oscillator to the external PCLK.
  • 0 in reply to Palaniappan Manickam
    Guru 29720 points

    Hi Palaniappan-san,

    I had thought as you commented however actual behavior wasn't.

    CML output of DS90UB913A-Q1 wasn't synchronized with external PCLK although PCLK was provided.
    On the other hand, CML output was normally synchronized with PCLK when connecting to Deserializer(DS90UB914A-CXEVM) with DS90UB913A-CXEVM,
    Could you confirm with DS90UB913A-CXEVM to reproduce the issue?

    Best Regards,
    Yaita / Japan disty

  • 0 in reply to K.Yaita
    Guru 29720 points

    Palaniappan-san,

    Could you support for this inquiry?
    Your support would be appreciated.

    Best Regards,
    Yaita

  • 0 in reply to K.Yaita
    TI__Genius 10475 points
    Yaita-san,
    Just trying to understand what is the concern here. The customer can measure the PCLK quality at the source and also monitor the CMLOUT for the quality of the signal coming out of the serializer.
  • 0 in reply to Palaniappan Manickam
    Guru 29720 points

    Palaniappan-san,

    The background of the question is my customer considers to test output waveform quality of his system in manufacturing process without connecting deserializer board that 914A is mounted.
    My customer designs only serializer boards and deserializer boards are designed by another vendor.

    Should we consider as it isn't possible to test output waveform quality in PCLK mode only with serializer board?
    If it isn't possible, we should inform it to my customer.

    Best Regards,
    Yaita

  • 0 in reply to K.Yaita
    TI__Genius 10475 points
    I am not sure I understand. They're measuring the CMLOUT on the deserializer correct? The CMLOUT pin is on the deserializer side showing the adaptive equalized output of the serial data stream at the other end.
  • 0 in reply to Palaniappan Manickam
    Guru 29720 points

    Hi Palaniappan-san,

    >They're measuring the CMLOUT on the deserializer correct?
    No, they measured CML output (DOUT+ / DOUT-) of DS90UB913A-Q1. (Sorry.. It is confusable as you said.)
    They put AC coupled capacitors at DOUT+ and DOUT- each and termination resistor between DOUT+ and DOUT-.

    So, May I have your further comments about the following?
    ----------------------------------------------
    I am evaluating DS90UB913A-CXEVM itself (not connected to Deserializer) and confirmed CML output frequency isn't synchronized with PCLK pin that is connected from pulse generator.
    It seems fixed 50MHz internal oscillator is used in this case.
    Is it expected behavior?
    If the answer is yes, how to synchronize CML output with PCLK pin?
    ----------------------------------------------

    Best Regards,
    Yaita

  • 0 in reply to K.Yaita
    TI__Genius 10475 points
    Yaita-san,
    It is expected that the 913A device switches from the internal oscillator mode to external PCLK when the PCLK is detected and register 0x03[1] is set to 0. Can you confirm this register value?
    You can check the datasheet for information about this register bit.
  • 0 in reply to Palaniappan Manickam
    Guru 29720 points

    Palaniappan-san,

    The default value of 0x03[1] is 0 and we didn't access registers of DS90UB913A-Q1 in this evaluation.
    I had thought as you commented however actual behavior wasn't.

    Could you apply 25 MHz PCLK to DS90UB913A-CXEVM and observe the FPD LNK III output using an oscilloscope? 
    Please let me know if FPD LINK III output is synchronized to the PCLK.

    Best Regards,
    Yaita

  • 0 in reply to K.Yaita
    TI__Genius 10475 points
    Yaita-san,

    Can you confirm by register read on the 913A the clock related bits are set as expected? For eg, register 0x03, 0x35. If 0x03[1] is indeed set to '1' then 0x35[1] will control the lock to external oscillator and 0x35[0] will allow internal clock to goto the PLL or the external clock. Refer to the datasheet for details.

    Also make sure the external clock you think you are providing is actually getting into the device by probing the pad on the board closer to the device.
  • 0 in reply to Palaniappan Manickam
    Guru 29720 points

    Palaniappan-san,

    I attached dump list of DS90UB913A register (not connected to DS90UB914A-CXEVM in this case).


    I confirmed 0x03[1] is set to "0", so It is expected that the 913A device switches from the internal oscillator mode to external PCLK when the PCLK is detected, however actual behavior wasn't true..
    I also confirmed the external PCLK is actually getting into the device. Please see the following waveform.

    1) Without DS90UB914A-CXEVM: PCLK(Yellow) and FPD LNK III output (Blue) were not synchronized


    2) With DS90UB914A-CXEVM: PCLK(Yellow) and FPD LNK III output (Blue) were synchronized


    I would like to know how to synchronize FPD LNK III output with PCLK when using only DS90UB913A-CXEVM itself (not connected to DS90UB914A-CXEVM).

    Best Regards,
    Yaita