DP83822IF: DP83822IF

Madhusoodana Bairy6

Part Number: DP83822IF

Hi,

We are using TI's DP83822IF Ethernet PHY in one of our design. We are able to read the PHY address but the link is not coming up. For LED_1 / GPIO1 pin (pin 24), it is said in datasheet that 'This pin must have a pulldown or pullup external resistor when not used to prevent bootstrapping to MODE 2 or MODE 3'. Could not understand this properly (mainly 2nd part of the statement).
Please suggest on other possibilities also, if any.

Best Regards,
Madhusoodana Bairy

over 7 years ago

0 Ross Pimentel over 7 years ago

TI__Mastermind 23675 points

Hi Madhusoodana,

Please hard tie LED_1 to either VDD or GND using a pull-up or pull-down resistor.
This pin should not be floating.
Do you have a schematic to share?
Can you read and write registers using MDIO/MDC?
Have you followed our troubleshooting guide:
www.ti.com/.../snla266.pdf

0 Madhusoodana Bairy6 over 7 years ago in reply to Ross Pimentel

Intellectual 680 points

Hi Ross,

Thanks for your response.
We are able to make link up and 100Mbps is working fine (issue was swapping of the 2 EMAC's mapping to 2 PHYs).
However, we are facing RMII reference clock issue with few processors. Even though we have configured it as input and flashed same code for all boards, few processors are (directly from BGA ball to series termination resistor pad) giving 50MHz output. Any known issue on this ??

Best Regards,
Madhusoodana Bairy

0 Ross Pimentel over 7 years ago in reply to Madhusoodana Bairy6

TI__Mastermind 23675 points

Hi Madhusoodana,

The DP83822 is outputting the clock or the processor is outputting the clock?
If you have processor issues you will need to reach out to the team supporting the processor.

0 Madhusoodana Bairy6 over 7 years ago in reply to Ross Pimentel

Intellectual 680 points

Hi,
Thanks for your response.

Processor is outputting the clock.

One more thing that we want to get confirmed is on power-up timing. Below two screenshots are from PHY datasheet page no. 15 and 16. It is bit confusing the timing between power and reset signal (between 2 pictures). Also, whether VDDIO and AVD can be powered up at the same time ?

Best Regards,
Madhusoodana Bairy

0 Ross Pimentel over 7 years ago in reply to Madhusoodana Bairy6

TI__Mastermind 23675 points

Hi Madhusoodana,

VDDIO and AVD can come up at the same time.
RESET_N is controlled by the PHY at power-up. When POR completes, it releases control of RESET_N pin and the user can have access to it.
For the second image it is just showing that the user can apply RESET_N any time after the supplies are stable. It shows how long the RESET pulse should be.

0 Madhusoodana Bairy6 over 7 years ago in reply to Ross Pimentel

Intellectual 680 points

Hi Ross,

Thanks for your response.
"RESET_N is controlled by the PHY at power-up" - Whether we have to ensure we are not pulling reset line low externally at power up ? (we are using an AND gate and this gate's output is fed to reset pin).
Also, whether we can have RC circuit for this reset pin (capacitor is not mounted though) ?

Best Regards,
Madhusoodana Bairy

0 Ross Pimentel over 7 years ago in reply to Madhusoodana Bairy6

TI__Mastermind 23675 points

You can pull the pin low if you would like.
This is allowed.
Yes, you can have RC on reset pin.

0 Madhusoodana Bairy6 over 7 years ago in reply to Ross Pimentel

Intellectual 680 points

Hi Ross,

Thanks for your response.
So you are saying that even if we pull the reset line low, PHY operation won't be effected at power up ? Because we are having 400ms delay between PHY power-up & Reset high (since we are driving a GPIO to AND gate, as i mentioned earlier). This is exceeding 200ms limit for MDC as in the timing diagram and Ethernet is not working currently. So, I think we have to reduce this 400ms timing. Correct ?

Best Regards,
Madhusoodana Bairy

0 Ross Pimentel over 7 years ago in reply to Madhusoodana Bairy6

TI__Mastermind 23675 points

Hi Madhusoodana,

You can keep the RESET pulled low as long as you like.
It might be confusing in the diagram. For the power-up, the RESET_N is what the PHY is controlling by itself.
You can keep holding this line low though, there is no timing requirement on it.
If you keep RESET low though, you cannot access MDIO/MDC because the PHY will remain in RESET state.

0 Madhusoodana Bairy6 over 7 years ago in reply to Ross Pimentel

Intellectual 680 points

Hi Ross,

Thanks for your response.
We are seeing 3 seconds delay between PHY Reset and MDC. Is this ok ? Because the parameter "Post power-up stabilization time prior to MDC preamble for register accesses" as in datasheet says MDC should be pulsing after max. 200ms of power-up.
Also, is there anything that we have to take care on Reset and MDIO bus, if we are driving these for 2 Ethernet PHYs ?

Best Regards,
Madhusoodana Bairy

0 Ross Pimentel over 7 years ago in reply to Madhusoodana Bairy6

TI__Mastermind 23675 points

Hi Madhusoodana,

Yes, it is ok to wait 3 seconds until you send MDC out.
You just need to wait a max 200ms and if you want to wait longer you can do so.
Some people don't even use MDIO/MDC so for that case it is indefinite.

For two PHYs, just be sure that you set them for different PHY IDs.
Besides that you should be good to go!

0 Madhusoodana Bairy6 over 7 years ago in reply to Ross Pimentel

Intellectual 680 points

Hi Ross,

Thanks for your response and sorry for the delay.

We are able to make it up.

Regards,
Madhusoodana Bairy

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DP83822IF: DP83822IF